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mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp description the M37753M8C-XXXFP is a single-chip microcomputer designed with high-performance cmos silicon gate technology. this is housed in a 80-pin plastic molded qfp. this microcomputer has a cpu and a bus interface unit. the cpu is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing, and the bus interface unit enhances the memory access efficiency to execute instructions fast. in addition to the 7700 family basic instructions, the m37753m8c- xxxfp has 6 special instructions which contain instructions for signed multiplication/division; these added instructions improve the servo arithmetic performance to control hard disk drives and so on. this microcomputer also include the rom, ram, multiple-function timers, motor control function, serial i/o, a-d converter, d-a con- verter, and so on. the differences between M37753M8C-XXXFP, m37753m8c-xxxhp, m37753s4cfp and m37753s4chp are listed in the table on the next page: the internal rom, usable processor mode, and package. therefore, the following descriptions will be for the m37753m8c- xxxfp unless otherwise noted. distinctive features ? number of basic machine instructions .................................... 109 (103 basic instructions of 7700 family + 6 special instructions) ? memory size rom ................................................ 60 kbytes ram ................................................ 2048 bytes ? instruction execution time the fastest instruction at 40 mhz frequency ...................... 100 ns ? single power supply ....................................................... 5v 10 % ? low power dissipation (at 40 mhz frequency) ....... 125 mw (typ.) ? interrupts ............................................................ 21 types, 7 levels ? multiple-function 16-bit timer ................................................... 5+3 (three-phase motor drive waveform or pulse motor control wave- form output) ? serial i/o (uart or clock synchronous) ...................................... 2 ? 10-bit a-d converter ............................................ 8-channel inputs ? 8-bit d-a converter ............................................ 2-channel outputs ? 12-bit watchdog timer ? programmable input/output (ports p0p8) .......................................................................... 68 application control devices for personal computer peripheral equipment such as cd-rom drives, hard disk drives, high density fdd, printers control devices for office equipment such as copiers and facsimiles control devices for industrial equipment such as communication and measuring instruments control devices for equipment required for motor control such as in- verter air conditioner and general purpose inverter M37753M8C-XXXFP pin configuration (top view) outline 80p6n-a preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 30 29 28 27 26 25 p7 0 /an 0 ? p6 7 /tb2 in ? p6 6 /tb1 in ? p6 2 /int 0 ? p6 1 /ta4 in ? p6 0 /ta4 out /rtp1 3 ? p5 7 /ta3 in /ki 3 ? p5 6 /ta3 out /ki 2 /rtp1 2 ? p5 5 /ta2 in /ki 1 /u/rtp1 1 ? p5 4 /ta2 out /ki 0 /v/rtp1 0 ? p5 3 /ta1 in /w/rtp0 3 ? p5 2 /ta1 out /u/rtp0 2 ? p5 1 /ta0 in /v/rtp0 1 ? p5 0 /ta0 out /w/rtp0 0 ? p4 7 ? p4 6 ? p4 5 ? p4 4 ? p4 3 ? p4 2 / f 1 ? p4 1 /rdy ? 64 63 62 61 60 59 58 57 56 55 54 53 52 51 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p6 5 /tb0 in ? p6 4 /int 2 ? p6 3 /int 1 ? ? p4 0 /hold ? byte cnv ss ? reset ? x in ? x out ? e v ss ? p3 3 /hlda ? p3 2 /ale ? p3 1 /bhe ? p3 0 /r/w ? p2 7 /a 23 /d 7 ? p2 6 /a 22 /d 6 ? p2 5 /a 21 /d 5 ? p2 4 /a 20 /d 4 ? p2 3 /a 19 /d 3 ? p2 2 /a 18 /d 2 ? p2 1 /a 17 /d 1 ? p2 0 /a 16 /d 0 ? p1 7 /a 15 /d 15 ? p1 6 /a 14 /d 14 ? p1 5 /a 13 /d 13 ? p1 4 /a 12 /d 12 ? p1 3 /a 11 /d 11 ? p1 2 /a 10 /d 10 ? p1 1 /a 9 /d 9 ? p1 0 /a 8 /d 8 ? p0 7 /a 7 ? p0 6 /a 6 ? p0 5 /a 5 ? p0 4 /a 4 ? p0 3 /a 3 ? p0 2 /a 2 ? p0 1 /a 1 ? p0 0 /a 0 ? p8 7 /t x d 1 ? p8 6 /r x d 1 ? p8 5 /clk 1 ? p8 4 /cts 1 /rts 1 /da 1 /int 4 p8 3 /t x d 0 ? p8 2 /r x d 0 /clks 0 ? p8 1 /clk 0 ? v cc av cc v ref ? av ss v ss p7 7 /an 7 /ad trg ? p7 6 /an 6 ? p7 5 /an 5 ? p7 4 /an 4 ? p7 3 /an 3 ? p7 2 /an 2 ? p7 1 /an 1 ? p8 0 /cts 0 /rts 0 /clks 1 /da 0 /int 3 /ki 4 ? M37753M8C-XXXFP or m37753s4cfp
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 2 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer m37753m8c-xxxhp pin configuration (top view) 26 27 ? p4 2 / f 1 ? p4 1 /rdy ? p4 0 /hold ? byte cnv ss ? reset ? x in ? x out ? e v ss ? p3 3 /hlda ? p3 2 /ale ? p3 1 /bhe ? p3 0 /r/w 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 79 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ? p8 6 /r x d 1 ? p8 7 /t x d 1 ? p0 0 /a 0 ? p0 1 /a 1 ? p0 2 /a 2 p8 5 /clk 1 ? p8 4 /cts 1 /rts 1 /da 1 /int 4 ? p8 3 /t x d 0 ? p8 2 /r x d 0 /clks 0 ? p8 1 /clk 0 ? v cc av cc v ref ? av ss v ss p7 7 /an 7 /ad trg ? m37753m8c-xxxhp or m37753s4chp p7 6 /an 6 ? p7 5 /an 5 ? p7 4 /an 4 ? p7 3 /an 3 ? p7 2 /an 2 ? p7 1 /an 1 ? p7 0 /an 0 ? p6 7 /tb2 in ? p8 0 /cts 0 /rts 0 /clks 1 /da 0 /int 3 /ki 4 ? 51 52 ? p2 7 /a 23 /d 7 ? p2 6 /a 22 /d 6 ? p2 5 /a 21 /d 5 ? p2 4 /a 20 /d 4 ? p2 3 /a 19 /d 3 ? p2 2 /a 18 /d 2 ? p2 1 /a 17 /d 1 ? p2 0 /a 16 /d 0 ? p1 7 /a 15 /d 15 ? p1 6 /a 14 /d 14 ? p1 5 /a 13 /d 13 ? p1 4 /a 12 /d 12 ? p1 3 /a 11 /d 11 ? p1 2 /a 10 /d 10 ? p1 1 /a 9 /d 9 ? p1 0 /a 8 /d 8 ? p0 7 /a 7 ? p0 6 /a 6 ? p0 5 /a 5 ? p0 4 /a 4 ? p0 3 /a 3 53 54 55 56 57 58 59 60 21 22 23 24 25 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 p4 3 ? p6 6 /tb1 in ? p6 5 /tb0 in ? p6 4 /int 2 ? p6 1 /ta4 in ? p6 0 /ta4 out /rtp1 3 ? p5 7 /ta3 in /ki 3 ? p5 6 /ta3 out /ki 2 /rtp1 2 ? p5 5 /ta2 in /ki 1 /u/rtp1 1 ? p5 4 /ta2 out /ki 0 /v/rtp1 0 ? p5 3 /ta1 in /w/rtp0 3 ? p5 2 /ta1 out /u/rtp0 2 ? p5 1 /ta0 in /v/rtp0 1 ? p5 0 /ta0 out /w/rtp0 0 ? p4 7 ? p4 6 ? p4 5 ? p4 4 ? p6 3 /int 1 ? p6 2 /int 0 ? outline 80p6q-a differences between M37753M8C-XXXFP, m37753m8c-xxxhp, m37753s4cfp, and m37753s4chp product M37753M8C-XXXFP m37753m8c-xxxhp m37753s4cfp m37753s4chp internal rom equipped (60 kbytes) not equipped (external rom) usable processor mode ? single-chip mode ? memory expansion mode ? microprocessor mode ? microprocessor mode package 80-pin qfp (80p6n-a) 80-pin fine pitch qfp (80p6q-a) 80-pin qfp (80p6n-a) 80-pin fine pitch qfp (80p6q-a)
3 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer p1 (8) input/output port p1 p0 (8) input/output port p0 rom 60 kbytes p8(8) p7(8) p6(8) p5(8) p4(8) input/output port p4 p3(4) p2 (8) input/output port p8 input/output port p7 input/output port p6 input/output port p5 input/output port p3 clock generating circuit instruction register(8) ram 2048 bytes timer ta0(16) timer ta1(16) timer ta2(16) timer ta3(16) timer tb0(16) timer tb1(16) timer tb2(16) watchdogtimer uart0(9) uart1(9) a-d converter(10) d-a 0 converter(8) d-a 1 converter(8) timer ta4(16) address bus data bus(even) data buffer db h (8) data buffer db l (8) instruction queue buffer q 0 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) incrementer(24) program address register pa(24) data address register da(24) processor status register ps(11) direct page register dpr(16) stack pointer s(16) incrementer/decrementer(24) program counter pc(16) program bank register pg(8) data bank register dt(8) index register y(16) index register x(16) accumulator b(16) accumulator a(16) arithmetic logic unit(16) input buffer register ib(16) data bus(odd) x in reset input reset (5v) v cc cnv ss (0v) av ss (5v) av cc reference voltage input (0v) v ss clock output x out v ref clock input e enable output input/output port p2 bus width select input byte block diagram
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 4 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer number of basic machine instructions instruction execution time memory size input/output ports (note 2) multiple-function timers serial i/o a-d converter d-a converter watchdog timer dead-time timer interrupts clock generating circuit supply voltage power dissipation input/output characteristic memory expansion operating temperature range device structure package rom (note 1) ram p0Cp2, p4Cp8 p3 ta0, ta1, ta2, ta3, ta4 tb0, tb1, tb2 functions of M37753M8C-XXXFP functions parameter 109 100 ns (the fastest instruction at external clock 40 mhz frequency) 60 kbytes 2048 bytes 8-bit 8 4-bit 1 16-bit 5 16-bit 3 (uart or clock synchronous serial i/o) 2 10-bit 1 (8 channels) 8-bit 2 12-bit 1 8-bit 3 5 external types, 16 internal types (each interrupt can be set to priority levels 0C7.) built-in (externally connected to a ceramic resonator or quartz crystal resonator) 5 v10 % 125 mw(at external clock 40 mhz frequency) 5 v 5 ma maximum 16 mbytes C20 to 85 c cmos high-performance silicon gate process 80-pin plastic molded qfp input/output withstand voltage output current notes 1: the m37753s4cfp and the m37753s4chp are not equipped with rom. 2: input/output ports for the m37753s4cfp and the m37753s4chp are as shown below : ? p5Cp8 (8-bit 4) ? p4 (5-bit 1)
5 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer supply 5 v10 % to v cc and 0 v to v ss . this pin controls the processor mode. connect to v ss for single-chip mode or memory expansion mode. connect to v cc for microprocessor mode and external rom version. this is reset input pin. the microcomputer is reset when supplying l level to this pin. these are i/o pins of internal clock generating circuit. connect a ceramic or quartz- crystal resonator between x in and x out . when an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. data or instruction read, data write are performed when output from this pin is l. this pin determines whether the external data bus is 8-bit width or 16-bit width for memory expansion mode or microprocessor mode. the width is 16 bits when l signal inputs and 8 bits when h signal inputs. power supply for the a-d converter and the d-a converter. connect av cc to v cc and av ss to v ss externally. this is reference voltage input pin for the a-d converter and the d-a converter. in single-chip mode, port p0 is an 8-bit i/o port. this port has an i/o direction register and each pin can be programmed for input or output. these ports are in the input mode when reset. address (a 0 Ca 7 ) is output in memory expansion mode or microprocessor mode. in single-chip mode, these pins have the same functions as port p0. when the byte pin is set to l in memory expansion mode or microprocessor mode and external data bus is 16-bit width, high-order data (d 8 Cd 15 ) is input or output if e output is l and an address (a 8 Ca 15 ) is output if e output is h. when the byte pin is set to h and an external data bus is 8-bit width, only address (a 8 Ca 15 ) is output. in single-chip mode, these pins have the same functions as port p0. in memory expansion mode or microprocessor mode, low-order data (d 0 Cd 7 ) is input or output when e output is l and an address (a 16 Ca 23 ) is output when e output is h. in single-chip mode, these pins have the same functions as port p0. in memory expansion mode or microprocessor mode, r/w, bhe , ale, and hlda signals are output. in single-chip mode, these pins have the same functions as port p0. in memory expansion mode or micro processor mode, p4 0 , p4 1 , and p4 2 become hold and rdy input pins, and clock f 1 output pin respectively. functions of other pins are the same as in single-chip mode. in memory expansion mode, p4 2 can be programmed as i/o port. in addition to having the same functions as port p0 in single-chip mode, these pins also function as i/o pins for timer a0, timer a1, timer a2, timer a3, output pins for motor drive waveform, and input pins for key input interrupt. in addition to having the same functions as port p0 in single-chip mode, these pins also function as the i/o pin for timer a4, input pins for external interrupt input int 0 , int 1 , and int 2 , and input pins for timer b0, timer b1, and timer b2, and output pin for motor drive waveform. in addition to having the same functions as port p0 in single-chip mode, these pins also function as input pins for a-d converter. in addition to having the same functions as port p0 in single-chip mode, these pins also function as i/o pins for uart0, uart1, output pins for d-a converter, and input pins for int 3 , int 4 . pin description functions input input input output output input input i/o i/o i/o i/o i/o i/o i/o i/o i/o input/ output name pin v cc , v ss cnv ss reset x in x out e byte (note) av cc , av ss v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 Cp3 3 p4 0 Cp4 7 p5 0 Cp5 7 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7 power supply cnv ss input reset input clock input clock output enable output bus width select input analog supply input reference voltage input i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 note: it is impossible to change the input level of the byte pin in each bus cycle. in other words, bus width cannot be switched dynamically. fix the input level of the byte pin to h or l according to the bus width used.
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 6 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer basic function blocks the M37753M8C-XXXFP and m37753m8c-xxxhp contain the fol- lowing devices on single chips: rom, ram, cpu, bus interface unit, timers, uart, a-d converter, d-a converter, i/o ports, clock gener- ating circuit and others. each of these devices is described below. memory the memory map is shown in figure 1. the address space is 16 mbytes from addresses 0 16 to ffffff 16 . the address space is di- vided into 64-kbyte units called banks. the banks are numbered from 0 16 to ff 16 . internal rom, internal ram, and control registers for internal periph- eral devices are assigned to bank 0 16 . the 60-kbyte area from addresses 1000 16 to ffff 16 is the internal rom. addresses ffd2 16 to ffff 16 are the reset and interrupt vector addresses and contain the interrupt vectors. refer to the section on interrupts for details. the 2048-byte area from addresses 80 16 to 87f 16 contains the in- ternal ram. in addition to storing data, the ram is used as stack dur- ing a subroutine call, or interrupts. assigned to addresses 0 16 to 7f 16 are peripheral devices such as i/o ports, a-d converter, d-a converter, uart, timer, and interrupt control registers. additionally the internal rom area can be modified by software. refer to the section on rom area modification function for details. a 256-byte direct page area can be allocated anywhere in bank 0 16 using the direct page register dpr. in direct page addressing mode, the memory in the direct page area can be accessed with two words thus reducing program steps. note: internal rom area can be modified. (refer to the section on rom area modification function.) 000000 16 000000 16 000000 16 00007f 16 00087f 16 00ffff 16 00fffe 16 00ffd2 16 000080 16 00ffff 16 bank 0 16 bank 1 16 010000 16 01ffff 16 ff0000 16 ffffff 16 internal ram 2048 bytes peripherai devices control registers interrupt vector table a? int 3 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 watchdog timer brk instruction zero divide see fig. 2 for further information int 1 int 0 dbc reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? bank ff 16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? internal rom 60 kbytes 001000 16 fe0000 16 feffff 16 bank fe 16 ? ? ? ? ? ? ? 00007f 16 int 4 fig. 1 memory map
7 mitsubishi microcomputers M37753M8C-XXXFP , m37753m8c-xxxhp m37753s4cfp , m37753s4chp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 2 location of peripheral devices and interrupt control registers 000000 000001 000002 000003 000004 000005 000006 000007 000008 000009 00000a port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p8 direction register a-d control register 0 a-d control register 1 a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 5 a-d register 6 a-d register 7 uart0 transmit/receive mode register uart0 baud rate register uart0 transmit buffer register uart0 transmit/receive control register 0 uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart1 receive buffer register 00000b 00000c 00000d 00000e 00000f 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001a 00001b 00001c 00001d 00001e 00001f 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002a 00002b 00002c 00002d 00002e 00002f 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003a 00003b 00003c 00003d 00003e 00003f 000040 000041 000042 000043 000044 000045 000046 000047 000048 000049 00004a count start register one-shot start register up-down register timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 processor mode register 1 watchdog timer register watchdog timer frequency select register comparator function select register comparator result register d-a register 0 d-a register 1 particular function select register 0 particular function select register 1 int 3 interrupt control register a-d interrupt control register uart0 trasmit interrupt control register uart0 receive interrupt control register uart1 trasmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register 00004b 00004c 00004d 00004e 00004f 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005a 00005b 00005c 00005d 00005e 00005f 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006a 00006b 00006c 00006d 00006e 00006f 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007a 00007b 00007c 00007d 00007e 00007f int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register address (hexadecimal notation) address (hexadecimal notation) port p0 register port p1 register port p0 direction register port p1 direction register port p2 register port p3 register port p2 direction register port p3 direction register waveform output mode register dead-time timer pulse output data register 1 pulse output data register 0 timer a write register reserved area (note) reserved area (note) int 4 interrupt control register note: do not write to this address.
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 8 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer central processing unit (cpu) the cpu has ten registers and is shown in figure 3. each of these registers is described below. accumulator a (a) accumulator a is the main register of the microcomputer. it consists of 16 bits and the low-order 8 bits can be used separately. the data length flag m determines whether the register is used as 16-bit reg- ister or as 8-bit register. it is used as a 16-bit register when flag m is 0 and as an 8-bit register when flag m is 1. flag m is a part of the processor status register (ps) which is described later. data operations such as calculations, data transfer, input/output, etc., is executed mainly through the accumulator. accumulator b (b) accumulator b has the same functions as accumulator a, but the use of accumulator b requires more instruction bytes and execution cycles than accumulator a. index register x (x) index register x consists of 16 bits and the low-order 8 bits can be used separately. the index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. it is used as a 16-bit register when flag x is 0 and as an 8-bit register when flag x is 1. flag x is a part of the processor status register (ps) which is described later. in index addressing mode, register x is used as the index register and the contents of this address is added to obtain the real address. index register x functions as a pointer register which indicates an address of data table in instructions mvp, mvn, rmpa (repeat multiply and accumulate). index register y (y) index register y consists of 16 bits and the low-order 8 bits can be used separately. the index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. it is used as a 16-bit register when flag x is 0 and as an 8-bit register when flag x is 1. flag x is a part of the processor status register (ps) which is described later. in index addressing mode, register y is used as the index register and the contents of this address is added to obtain the real address. index register y functions as a pointer register which indicates an address of data table in instructions mvp, mvn, rmpa (repeat multiply and accumulate). 15 7 0 15 7 0 15 7 0 15 7 0 15 0 15 0 15 0 15 7 0 00000 ipl 2 ipl 1 ipl 0 nvmxd i zc dpr pc s y h y l x h x l b h b l a h a l accumulator a accumulator b index register x index register y stack pointer s program counter pc direct page register dpr processor status register ps carry flag zero flag interrupt disable flag decimal mode flag index register length flag data length flag overflow flag negative flag processor interrupt priority level ipl 70 70 pg program bank register pg data bank register dt dt fig. 3 register structure
9 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer stack pointer (s) stack pointer (s) is a 16-bit register. it is used during a subroutine call or interrupts. it is also used during stack, stack pointer relative, or stack pointer relative indirect indexed y addressing mode. program counter (pc) program counter (pc) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. there is a bus interface unit between the program memory and the cpu, so that the program memory is accessed through bus interface unit. this is described later. program bank register (pg) program bank register is an 8-bit register that indicates the high-or- der 8 bits of the next program memory address to be executed. when a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (pg) is increased by 1. also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (pc) us- ing the branch instruction, the contents of the program bank register (pg) is increased or decreased by 1, so that programs can be writ- ten without worrying about bank boundaries. data bank register (dt) data bank register (dt) is an 8-bit register. with some addressing modes, the data bank register (dt) is used to specify a part of the memory address. the contents of data bank register (dt) is used as the high-order 8 bits of a 24-bit address. addressing modes that use the data bank register (dt) are direct indirect, direct indexed x indi- rect, direct indirect indexed y, absolute, absolute bit, absolute in- dexed x, absolute indexed y, absolute bit relative, and stack pointer relative indirect indexed y. direct page register (dpr) direct page register (dpr) is a 16-bit register. its contents is used as the base address of a 256-byte direct page area. the direct page area is allocated in bank 0 16 , but when the contents of dpr is ff01 16 or greater, the direct page area spans across bank 0 16 and bank 1 16 . all direct addressing modes use the contents of the direct page register (dpr) to generate the data address. if the low-order 8 bits of the direct page register (dpr) is 00 16 , the number of cycles required to generate an address is minimized. normally the low-order 8 bits of the direct page register (dpr) is set to 00 16 . processor status register (ps) processor status register (ps) is an 11-bit register. it consists of a flag to indicate the result of operation and cpu interrupt levels. branch operations can be performed by testing the flags c, z, v, and n. the details of each bit of the processor status register are described below. 1. carry flag (c) the carry flag contains the carry or borrow generated by the alu af- ter an arithmetic operation. this flag is also affected by shift and ro- tate instructions. this flag can be set and reset directly with the sec and clc instructions or with the sep and clp instructions. 2. zero flag (z) the zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. this flag can be set and reset directly with the sep and clp instructions. 3. interrupt disable flag (i) when the interrupt disable flag is set to 1, all interrupts except ___ watchdog timer, dbc, and software interrupt are disabled. this flag is set to 1 automatically when there is an interrupt. it can be set and reset directly with the sei and cli instructions or sep and clp in- structions. 4. decimal mode flag (d) the decimal mode flag determines whether addition and subtraction are performed as binary or decimal. binary arithmetic is performed when this flag is 0. if it is 1, decimal arithmetic is performed with each word treated as 2- or 4- digit decimal. arithmetic operation is performed using four digits when the data length flag m is 0 and with two digits when it is 1. decimal adjust is automatically per- formed. (decimal operation is possible only with the adc and sbc instructions.) this flag can be set and reset with the sep and clp instructions.
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 10 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer 5. index register length flag (x) the index register length flag determines whether index register x and index register y are used as 16-bit registers or as 8-bit registers. the registers are used as 16-bit registers when flag x is 0 and as 8- bit registers when it is 1. this flag can be set and reset with the sep and clp instructions. 6. data length flag (m) the data length flag determines whether the data length is 16-bit or 8-bit. the data length is 16-bit when flag m is 0 and 8-bit when it is 1. this flag can be set and reset with the sem and clm instructions or with the sep and clp instructions. 7. overflow flag (v) the overflow flag is valid when addition or subtraction is performed with a word treated as a signed binary number. if data length flag m is 0, the overflow flag is set when the result of addition or subtrac- tion is outside the range between C32768 and +32767. if data length flag m is 1, the overflow flag is set when the result of addition or subtraction is outside the range between C128 and +127. it is reset in all other cases. the overflow flag can also be set and reset directly with the sep, and clv or clp instructions. additionally, the overflow flag is set when a result of unsigned/signed division exceeds the length of the register where the result is to be stored; the flag is also set when the addition result is outside range of C2147483648 to +2147483647 in the rmpa operation. 8. negative flag (n) the negative flag is set when the result of arithmetic operation or data transfer is negative (if data length flag m is 0, datas bit 15 is 1. if data length flag m is 1, datas bit 7 is 1.) it is reset in all other cases. it can also be set and reset with the sep and clp instruc- tions. 9. processor interrupt priority level (ipl) the processor interrupt priority level (ipl) consists of 3 bits and de- termines the priority of processor interrupts from level 0 to level 7. interrupt is enabled when the interrupt priority of the device request- ing interrupt (set using the interrupt control register) is higher than the processor interrupt priority. when interrupt is enabled, the current processor interrupt priority level is saved in a stack and the proces- sor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. refer to the section on interrupts for more details. note: fix bits 11 to 15 of the processor status register (ps) to 0. bus interface unit the cpu operates on the basis of internal clock f cpu frequency. in order to speed-up processing, a bus interface unit is used to pre- fetch instructions when the data bus is idle. the bus interface unit synchronizes the cpu and the bus and pre-fetches instructions. fig- ure 4 shows the relationship between the cpu and the bus interface unit. the bus interface unit controls buses to access memories easily. refer to bus cycle on the following pages. the bus interface unit has a program address register, a 3-byte instruction queue buffer, a data address register, and a 2-byte data buffer. the bus interface unit obtains an instruction code from memory and stores it in the instruction queue buffer, obtains data from memory and stores it in the data buffer, or writes the data form the data buffer to the memory. fig. 4 relationship between the cpu and the bus interface unit d' 8 ?' 15 cpu bus interface unit a' 0 ?' 23 control signal d' 0 ?' 7 d 8 ? 15 a 0 ? 23 bhe ale byte hold e r/w d 0 ? 7
11 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer figure 5 shows basic waveforms of the bus interface unit. the e sig- nal becomes l when the bus interface unit reads an instruction code or data from memory or when it writes data to memory. whether to perform read or write is controlled by the r/w signal. read is performed when the r/w signal is h state and write is per- formed when it is l state. waveform (1) in figure 5 is used to access a single byte or two bytes simultaneously. to read or write two bytes simultaneously, the first address accessed must be even. furthermore, when accessing an external memory area in memory expansion mode or microproces- sor mode, set the bus width select input pin (byte) to l (external data bus width = 16 bits). the internal memory area is always treated as 16-bit bus width regardless of byte. when performing 16-bit data read or write, if the conditions for simul- taneously accessing two bytes are not satisfied, waveform (2) is used to access each byte, one by one. however, when prefetching the instruction code, if the address of the instruction code is odd, only one byte is read in the instruction queue buffer. fig. 5 basic waveforms of bus interface unit (2) (1) e internal address bus (a 0 ? 23 ) internal data bus (d 0 ? 7 ) internal data bus (d 8 ? 15 ) data (odd) address (odd) address (even) data (even) invalid data invalid data e internal address bus (a 0 ? 23 ) internal data bus (d 0 ? 7 ) internal data bus (d 8 ? 15 ) address data (even) data (odd)
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 12 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer instruction code read, data read, and data write are described below. instruction code read will be described first. the cpu obtains instruction codes from the instruction queue buffer and executes them. the cpu notifies the bus interface unit that cpu is requesting an instruction code during an instruction code request cycle. if the requested instruction code is not yet stored in the instruc- tion queue buffer, the bus interface unit halts the cpu until it can store more instructions than requested in the instruction queue buffer. even if there is no instruction code request from the cpu, the bus interface unit reads instruction codes from memory and stores them in the instruction queue buffer when the instruction queue buffer is empty or when only one instruction code is stored and the bus is idle on the next cycle. this is referred to as instruction pre-fetching. normally, when reading an instruction code from memory, if the ac- cessed address is even, the next odd address is read together with the instruction code and stored in the instruction queue buffer. however, in memory expansion mode or microprocessor mode, if the bus width select input (byte) is h and external data bus width is 8 bits, and if the address to be read is in external memory area or is odd, only one byte is read and stored in the instruction queue buffer. data read and write are described below. the cpu notifies the bus interface unit when performing data read or write. at this time, the bus interface unit halts the cpu if the bus interface unit is already using the bus or if there is a request with higher priority. when data read or write is enabled, the bus interface unit performs data read or write. during data read, the cpu waits until the entire data is stored in the data buffer. the bus interface unit sends the address sent from the cpu to the address bus. then it reads the memory when the e sig- nal is l and stores the result in the data buffer. during data write, the cpu writes the data in the data buffer and the bus interface unit writes it to memory. therefore, the cpu can pro- ceed to the next step without waiting for write to complete. the bus interface unit sends the address sent from the cpu to the address bus. then, when the e signal is l, the bus interface unit sends the data in the data buffer to the data bus and writes it to memory. bus cycle the M37753M8C-XXXFP can select bus cycles shown in figures 6 and 7. central processing unit (cpu) running speed can be selected from low-speed running (clock f 1 12.5 mhz) and high-speed running (clock f 1 20 mhz); it is selected by bit 3 of processor mode register 1 (see figure 9). when accessing the external memory, the bus cycle is selected by bits 4 and 5 of processor mode register 1. when accessing the internal memory, the bus cycle is selected by bit 2 of processor mode register 0 (see figure 14). figure 8 shows output signals at 3- f access in high-speed running. the bhe signal becomes l when accessing the odd address. signals a 0 and bhe indicate the differences between 1-byte read in even address, 1-byte read in odd address, and simultaneous 2-byte read in even and odd address; these signals also indicate the differrences between 1-byte write in even address, 1-byte write in odd address, and simultaneous 2-byte write in even and odd ad- dress. the a 0 signal, which is bit 0 of address, becomes l when access- ing an even address. table 1. signals a 0 and bhe access of 1 byte in even address l h access of 1 byte in odd address h l simultaneous access of 2 bytes l l access method signal a 0 bhe
13 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer low-speed running ( f 1 12.5 mh z ) internal memory access 2- f access fig. 6 bus cycle selection (low-speed running) 2- f access 3- f access 4- f access external memory access * a : address r : read data w : write data f e ale read write 1 bus cycle=2 f a a w f e ale read write 1 bus cycle=2 f w a ar f e ale read write 1 bus cycle=3 f w a a r f e ale read write 1 bus cycle=4 f w a a r
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 14 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer high-speed running ( f 1 20 mh z ) internal memory access external memory access 3- f access fig. 7 bus cycle selection (high-speed running) 2- f access (note) 4- f access 5- f access 3- f access (note) * a : address r : read data w: write data ? : undefined note: refer to internal memory access bus cycle select bit (bit 2 of processor mode register 0 ; figure 14). f e ale read write 1 bus cycle=2 f a a ? f e ale read write 1 bus cycle=3 f w a a f e ale read write 1 bus cycle=3 f w a a r f e ale read write 1 bus cycle=4 f w a a r f e ale read write 1 bus cycle=5 f w a a r
15 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer access from even address access from odd address 1-byte read/write 2-byte read/write 1-byte read/write external data bus width = 16 bits external data bus width = 8 bits 2-byte read/write note: it becomes hi-z when reading, and it outputs undefined data when writing. fig. 8 output signals at 3- f access in high-speed running e bhe ale a 16 /d 0 ? 23 /d 7 a 8 /d 8 ? 15 /d 15 a 0 ? 7 a 0 ? 7 a 8 ? 15 a 16 ? 23 d 0 ? 7 f 1 e bhe ale a 16 /d 0 ? 23 /d 7 a 8 /d 8 ? 15 /d 15 a 0 ? 7 a 0 ? 7 a 8 ? 15 a 0 ? 7 a 8 ? 15 a 16 ? 23 d 0 ? 7 a 16 ? 23 d 0 ? 7 f 1 e bhe ale a 16 /d 0 ? 23 /d 7 a 8 /d 8 ? 15 /d 15 a 0 ? 7 a 0 ? 7 a 16 ? 23 a 16 ? 23 d 0 ? 7 f 1 e bhe ale a 16 /d 0 ? 23 /d 7 a 8 /d 8 ? 15 /d 15 a 0 ? 7 a 0 ? 7 a 16 ? 23 d 0 ? 7 a 8 ? 15 d 8 ? 15 f 1 e bhe ale a 16 /d 0 ? 23 /d 7 a 8 /d 8 ? 15 /d 15 a 0 ? 7 a 0 ? 7 a 8 ? 15 a 16 ? 23 d 0 ? 7 f 1 e bhe ale a 16 /d 0 ? 23 /d 7 a 8 /d 8 ? 15 /d 15 a 0 ? 7 a 0 ? 7 a 8 ? 15 a 0 ? 7 a 8 ? 15 a 16 ? 23 d 0 ? 7 a 16 ? 23 d 0 ? 7 f 1 e bhe ale a 16 /d 0 ? 23 /d 7 a 8 /d 8 ? 15 /d 15 a 0 ? 7 a 0 ? 7 a 16 ? 23 a 8 ? 15 d 8 ? 15 f 1 e bhe ale a 16 /d 0 ? 23 /d 7 a 8 /d 8 ? 15 /d 15 a 0 ? 7 a 0 ? 7 a 0 ? 7 a 16 ? 23 a 16 ? 23 d 0 ? 7 a 8 ? 15 d 8 ? 15 a 8 ? 15 f 1
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer 76543210 0 0 0 processor mode register 1 5f 16 address these bits must be ?0.? clock source for peripheral devices select bit (note) 0 : f 1 /2 1 : f 1 cpu running speed select bit 0 : high-speed running 1 : low-speed running bus cycle select bits in high-speed running 00 : 5- f access in high-speed running 01 : 4- f access in high-speed running 10 : 3- f access in high-speed running 11 : do not select. in low-speed running 00 : do not select. 01 : 4- f access in low-speed running 10 : 3- f access in low-speed running 11 : 2- f access in low-speed running clock source select bit 0 : f 1 = f(x in )/2 1 : f 1 = f(x in ) this bit must be ?.? note : when f 1 > 12.5 mhz, set bit 2 to ?.? fig. 9 processor mode register 1 bit configuration
17 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer interrupts table 2 shows the interrupt types and the corresponding interrupt vector addresses. reset is also treated as a type of interrupt and is discussed in this section, too. dbc is an interrupt used during debugging. interrupts other than reset, dbc, watchdog timer, zero divide, and brk instruction all have interrupt control registers. table 3 shows the addresses of the interrupt control registers and figure 10 shows the bit configuration of the interrupt control register. the interrupt request bit is automatically cleared by the hardware during reset or when processing an interrupt. also, interrupt request bits other than dbc and watchdog timer can be cleared by software. int 4 to int 0 are external interrupts; whether to cause an interrupt at the input level (level sense) or at the edge (edge sense) can be se- lected with the level/edge select bit. furthermore, the polarity of the interrupt input can be selected with the polarity select bit. in the int 3 external interrupt, the int 3 input, ki 3 to ki 0 inputs, or ki 4 to ki 0 inputs can be selected with bits 7 and 6 of int 3 interrupt con- trol register. timer and uart interrupts are described in the respective section. the priority of interrupts when multiple interrupts are caused simul- taneously is partially fixed by hardware, but, it can also be adjusted by software as shown in figure 11. the hardware priority is fixed as the following: reset > dbc > watchdog timer > other interrupts table 2. interrupt types and the interrupt vector addresses interrupts int 4 external interrupt int 3 external interrupt a-d uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 external interrupt int 1 external interrupt int 0 external interrupt watchdog timer dbc (do not select.) break instruction zero divide reset vector addresses 00ffd2 16 00ffd3 16 00ffd4 16 00ffd5 16 00ffd6 16 00ffd7 16 00ffd8 16 00ffd9 16 00ffda 16 00ffdb 16 00ffdc 16 00ffdd 16 00ffde 16 00ffdf 16 00ffe0 16 00ffe1 16 00ffe2 16 00ffe3 16 00ffe4 16 00ffe5 16 00ffe6 16 00ffe7 16 00ffe8 16 00ffe9 16 00ffea 16 00ffeb 16 00ffec 16 00ffed 16 00ffee 16 00ffef 16 00fff0 16 00fff1 16 00fff2 16 00fff3 16 00fff4 16 00fff5 16 00fff6 16 00fff7 16 00fff8 16 00fff9 16 00fffa 16 00fffb 16 00fffc 16 00fffd 16 00fffe 16 00ffff 16 fig. 10 interrupt control register bit configuration 76543210 interrupt priority level interrupt request bit (note 1) 0 : no interrupt 1 : interrupt 76543210 interrupt priority level interrupt request bit 0 : no interrupt 1 : interrupt polarity select bit 0 : set interrupt request bit at ??level for level sense and when changing from ??to ?? level for edge sense. 1 : set interrupt request bit at ??level for level sense and when changing from ??to ?? level for edge sense. level/edge select bit 0 : edge sense 1 : level sense key input interrupt select bits 1, 0 (only for int 3 interrupt control register) 0 0 : int 3 interrupt selected 0 1 : do not select. 1 0 : key input interrupt (ki 3 to ki 0 ) selected 1 1 : key input interrupt (ki 4 to ki 0 ) selected interrupt control register configuration for a-d converter, uart0, uart1, timer a0 to timer a4, and timer b0 to timer b2. note 1: the a-d conversion interrupt request bit becomes undefined after reset. clear this bit to ??before use of the a-d conversion interrupt. interrupt control register configuration for int 4 ?int 0 (note 2) . note 2: the contents of int 4 interrupt control register after reset cannot be changed unless bit 5 of the particular function select register 1 (see figure 15) is set to ?.?
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 18 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer table 3. addresses of interrupt control registers interrupt control registers int 4 interrupt control register int 3 interrupt control register a-d interrupt control register uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register addresses 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 the interrupt request bit and the interrupt priority level of each inter- rupt source are sampled and latched at each operation code fetch cycle while f biu is h. however, no sampling pulse is generated un- til the cycles whose number is selected by software has passed, even if the next operation code fetch cycle is generated. the detec- tion of an interrupt which has the highest priority is performed during that time. fig. 11 interrupt priority fig. 12 interrupt priority detection interrupts caused by a brk instruction and when dividing by zero are software interrupts and are not included in this list. other interrupts previously mentioned are a-d converter, uart, etc. interrupts. the priority of these interrupts can be changed by chang- ing the priority level in the corresponding interrupt control register by software. figure 12 shows a diagram of the interrupt priority detection circuit when an interrupt is caused, each interrupt device compares its own priority with the priority from above and if its own priority is higher, then it sends the priority below and requests the interrupt. if the pri- orities are the same, the one above has priority. this comparison is repeated to select the interrupt with the highest priority among the interrupts that are being requested. finally the selected interrupt is compared with the processor interrupt priority level (ipl) contained in the processor status register (ps) and the request is accepted if it is higher than ipl and the interrupt disable flag i is 0. the request is not accepted if flag i is 1. the reset, dbc, and watchdog timer interrupts are not affected by the interrupt dis- able flag i. when an interrupt is accepted, the contents of the processor status register (ps) is saved to the stack and the interrupt disable flag i is set to 1. furthermore, the interrupt request bit of the accepted interrupt is cleared to 0 and the processor interrupt priority level (ipl) in the processor status register (ps) is replaced by the priority level of the accepted interrupt. therefore, multi-level priority interrupts are possible by resetting the interrupt disable flag i to 0 and enable further interrupts. for reset, dbc, watchdog timer, zero divide, and brk instruction in- terrupts, which do not have an interrupt control register, the proces- sor interrupt level (ipl) is set as shown in table 4. watchdog timer dbc priority is determined by hardware a-d converter, uart, etc. interrupts priority can be changed with software inside 4 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 321 reset a-d uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 dbc watchdog timer ipl interrupt request level 0 interrupt disable flag i int 3 int 1 int 2 int 1 int 0 int 4
19 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer as shown in figure 13, there are three different interrupt priority de- tection time from which one is selected by software. after the se- lected time has elapsed, the highest priority is determined and is processed after the currently executing instruction has been com- pleted. the time is selected with bits 4 and 5 of the processor mode register 0 (address 5e 16 ) shown in figure 14. table 5 shows the relationship between these bits and the number of cycles. after a reset, the pro- cessor mode register 0 is initialized to 00 16. therefore, the longest time is automatically set, however, the shortest time must be se- lected by software. table 4. value set in processor interrupt level (ipl) during an interrupt interrupt types reset dbc watchdog timer zero divide brk instruction setting value 0 7 7 not change value of ipl. not change value of ipl. table 5. relationship between interrupt priority detection time select bit and number of cycles priority detection time select bit bit 5 0 0 1 bit 4 0 1 0 7 cycles of f biu 4 cycles of f biu 2 cycles of f biu number of cycles fig. 13 interrupt priority detection time operation code fetch cycle f biu sampling pulse priority detection time select one from 0 to 2 with bits 4 and 5 of processor mode register 0 ? ? ? ? ? ? ? ? ? ? 0 1 2
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 20 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 14 processor mode register 0 bit configuration notes 1: bits 2, 3, and 4 can be re-write after bit 5 (expansion function select bit) is set to ?.? 2: after bit 5 is set to ??once, bit 5 cannot be cleared to ??except external reset and software reset. 3: bits 6 and 7 are write-only bits and undefined at read. do not use seb or clb insturuction when setting bits 0?. transmit clock output pin select bit 00 : normal mode (output only to clk 0 ) 01 : plural clocks specified; output to clk 0 10 : plural clocks specified; output to clks 0 11 : plural clocks specified; output to clks 1 internal clock stop select bit at wit (note 1) 0 : clock for peripheral function and watchdog timer are operating at wit 1 : internal clock except that for oscillation circuit and watchdog timer are stopped at wit 76543210 particular function select register 1 (6d 16 ) watchdog timer? clock select bit (note 1) 0 : exclusive clock deviding circuit output (wf 512 , wf 32 ) is used as clock for watchdog timer. clock (wf 512 , wf 32 ) for watchdog timer does not change in hold. 1 : clock for peripheral device deviding circuit output (pf 512 , pf 32 ) is used as clock for watchdog timer. clock (pf 512 , pf 32 ) for watchdog timer changes in hold. watchdog timer exclusive clock dividing circuit is stopped. signal output stop select bit (note 1) refer to table 8. expansion function select bit (note 2) refer to figure 62. pull-up select bit 0 (note 3) 0 : with no pull-up for p5 7 , p5 6 , p5 5 , p5 4 1 : with pull-up for p5 7 , p5 6 , p5 5 , p5 4 pull-up select bit 1 (note 3) 0 : with no pull-up for p8 0 1 : with pull-up for p8 0 tc 1 tc 0 fig. 15 processor mode register 0 bit configuration note : when selecting low-speed running, set bit 2 to ?.? processor mode bits 00 : single-chip mode 01 : memory expansion mode 10 : microprocessor mode 11 : do not select. internal memory access bus cycle select bit (note) internal memory access condition in high-speed running 0 : 2- f access for internal ram, 3- f access for internal rom and sfr 1 : 2- f access for internal ram, internal rom, sfr software reset bit the microcomputer is reset when this bit is set to ?? interrupt priority detection time select bit 0 0 : select 0 in figure 13 0 1 : select 1 in figure 13 1 0 : select 2 in figure 13 test mode bit this bit must be ?.? clock f 1 output select bit 0 : no f 1 output 1 : f 1 output 76543210 0 processor mode register 0 (5e 16 )
21 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer the int 3 interrupt can function as the key input interrupt by setting bits 7 and 6 of the int 3 interrupt control register. the key input inter- rupt uses inputs ki 3 to ki 0 or inputs ki 4 to ki 0 . figure 10 shows the interrupt control register bit configuration. figure 15 shows the par- ticular function select register 1 bit configuration, and figure 16 shows the int 3 /key input interrupt input circuit block diagram. when the int 3 interrupt control registers bit 7 is 0 and its bit 6 is 0, a signal from the int 3 pin is connected to the int 3 interrupt con- trol circuit and int 3 external interrupt is normally performed. when the int 3 interrupt control registers bit 7 is 1 and its bit 6 is 0, signals from the ki 3 to ki 0 pins, which correspond to ports p5 7 to p5 4 , are inverted and then the logical sum of these signals is con- nected to the int 3 interrupt control circuit. in this case, the external interrupt which uses the ki 3 to ki 0 pins is performed. when the int 3 interrupt control registers bit 7 is 1 and its bit 6 is 1, signals from the ki 4 pin, which corresponds to port p8 0 , ki 3 to ki 0 pins, which correspond to ports p5 7 to p5 4 , are inverted and then the logical sum of these signals is connected to the int 3 interrupt control circuit. in this case, the external interrupt which uses the ki 4 to ki 0 pins is performed. when using the above key input interrupt, select the edge sense which uses the falling edge from h to l with the int 3 interrupt con- trol register so that an interrupt request can occur by inputting l to each of the ki 3 to ki 0 pins or the ki 4 to ki 0 pins. the interrupt vector is common to the int 3 interrupts one. additionally, pull-up resistor (transistors) can be added to the ki 4 to ki 0 pins by setting the con- tents of the particular function select register 1s bits 7 and 6 and setting 0 to each bit of the corresponding ports direction register. fig. 16 int 3 /key input interrupt input circuit block diagram pull-up select bit 1 pull-up select bit 0 key input interrupt select bit 0 (bit 6 of int 3 interrupt control register) port p8 0 direction register p5 7 /ki 3 pull-up transistor port p5 7 direction register port p5 6 direction register port p5 5 direction register port p5 4 direction register p8 0 /int 3 /ki 4 p5 6 /ki 2 p5 5 /ki 1 p5 4 /ki 0 int 3 interrupt control register (address 6f 16 ) when the key input interrupt is selected, select the edge sense which uses falling edge from ??to ?? interrupt control circuit int 3 interrupt request key input interrupt select bit 1 0 1 bit 7 of int 3 interrupt control register pull-up transistor pull-up transistor pull-up transistor
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 22 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer timer there are eight 16-bit timers. they are divided by type into timer a(5) and timer b(3). the timer i/o pins are multiplexed with i/o pins for port p5 and p6. to use these pins as timer input pins, the data direction register bit corresponding to the pin must be cleared to 0 to specify input mode. timer a figure 17 shows a block diagram of timer a. timer a has four modes: timer mode, event counter mode, one-shot pulse mode, and pulse width modulation mode. the mode is se- lected with bits 0 and 1 of the timer ai mode register (i = 0 to 4). each of these modes is described below. (1) timer mode [00] figure 18 shows the bit configuration of the timer ai mode register during timer mode. bits 0 and 1 of the timer ai mode register must be 0 in timer mode. bits 3, 4, and 5 are used to select the gate func- tion. bits 4 and 5 must be 0 when not selecting the gate function. bit 3 is ignored if bit 4 is 0. bits 6 and 7 are used to select the timer counter source. the counting of the selected clock starts when the count start bit is 1 and stops when it is 0. figure 19 shows the bit configuration of the count start bit. the counter is decremented, an interrupt is caused and the interrupt re- quest bit in the timer ai interrupt control register is set when the con- tents becomes 0000 16 . at the same time, the contents of the reload register is transferred to the counter and count is continued. when data is written to timer ai register with timer ai halted, the same data is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the new data is reloaded from the reload register to the counter at the next reload time and counting continues. the contents of the counter can be read at any time. when the value set in the timer ai register is n, the timer frequency dividing ratio is 1/(n+1). fig. 17 block diagram of timer a ?timer ?one-shot ?pulse width modulation count start bit (40 16 ) down count data bus (odd) data bus (even) reload register(16) counter(16) (lower 8 bits) (higher 8 bits) always decremented except in event count mode timer a0 47 16 46 16 timer a1 49 16 48 16 timer a2 4b 16 4a 16 timer a3 4d 16 4c 16 timer a4 4f 16 4e 16 up/down toggle flip-flop up-down bit (44 16 ) polarity selection a ddresses external trigger event counter tai in (i = 0?) tai out (i = 0?) timer(gate function) clock source selection pulse output pf 2 pf 16 pf 64 pf 512 note: perform write and read to/from timer ai register in the condition of 16-bit data length : data length flag (m) = 0.
23 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer pulse output function when bit 2 of the timer ai mode register is 1, the output is gener- ated from tai out pin. the output is toggled each time the contents of the counter reaches to 0000 16 . when the contents of the count start bit is 0, l is output from tai out pin. when bit 2 is 0, tai out can be used as a normal port pin. when bit 4 is 0, tai in can be used as a normal port pin. gate function when bit 4 is 1, counting is performed only while the input signal from the tai in pin is h or l as shown in figure 20. therefore, this can be used to measure the pulse width of the tai in input signal. whether to count while the input signal is h or while it is l is deter- mined by bit 3. if bit 3 is 1, counting is performed while the tai in pin input signal is h and if bit 3 is 0, counting is performed while it is l. when bit 5 is 0, counting restarts from the value which is contained at restarting (gate function 0 [no reload]) and an overflow occurs (n + 1) cycles of the count source later. figure 21 shows that operation. when bit 5 is 1, counting restarts from the value which is obtained by reload at restarting (gate function 1 [reload]) and the first overflow occurs (n + 2) cycles of the count source later. figure 22 shows that operation. after that, while the input signal from the tai in pin keeps valid level, an overflow occurs at (n + 1)- cycle intervals. make sure to set the value of 1 or more to n. when gate functions are used, the duration of h or l on the tai in pin must be 2 or more cycles of the timer count source. 0 0 : always 00 in timer mode 0 : no pulse output (tai out is normal port pin) 1 : pulse output 0 : no gate function (tai in is normal port pin) 1 0 : count only while tai in input is l 1 1 : count only while tai in input is h 0 : gate function 0 (no reload) 1 : gate function 1 (reload) ; note clock source select bit 0 0 : select pf 2 0 1 : select pf 16 1 0 : select pf 64 1 1 : select pf 512 timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register 7 00 6543210 addresses 56 16 57 16 58 16 59 16 5a 16 note: when selecting no gate function (bit 4 = 0) in timer mode, fix bit 5 to 0. fig. 18 timer ai mode register bit configuration during timer mode
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 24 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 19 count start flag bit configuration fig. 20 count waveform when gate function is available 76543210 timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit timer b0 count start bit timer b1 count start bit timer b2 count start bit count start register (stop at ?? start at ?? address 40 16 selected clock source pfi tai in bit 4 bit 3 10 timer mode register bit 4 bit 3 11 timer mode register
25 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 21 timer operation example with gate function 0 (no reload) selected count start count stop count stop overflow count start flag cleared by accepting the interrupt request or by software input level to tai in pin tai interrupt request bit ?? ?? invalid level valid level time ffff 16 n count start reloaded duration count stop reloaded overflow count start flag cleared by accepting the interrupt request or by software input level to tai in pin tai interrupt request bit ?? ?? invalid level valid level time ffff 16 n fig. 22 timer operation example with gate function 1 (reload) selected
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 26 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (2) event counter mode [01] figure 23 shows the bit configuration of the timer ai mode register during event counter mode. in event counter mode, bit 0 of the timer ai mode register must be 1 and bits 1 and 5 must be 0. the input signal from the tai in pin is counted when the count start bit shown in figure 19 is 1 and counting is stopped when it is 0. count is performed at the fall of the input signal when bit 3 is 0 and at the rise of the signal when it is 1. in event counter mode, whether to increment or decrement the count can be selected with the up-down bit or the input signal from the ta i out pin. when bit 4 of the timer ai mode register is 0, the up-down bit is used to determine whether to increment or decrement the count (decrement when the bit is 0 and increment when it is 1). figure 24 shows the bit configuration of the up-down register. when bit 4 of the timer ai mode register is 1, the input signal from the tai out pin is used to determine whether to increment or decre- ment the count. however, note that bit 2 must be 0 if bit 4 is 1. it is because if bit 2 is 1, tai out pin becomes an output pin to output pulses. the count is decremented when the input signal from the tai out pin is l and incremented when it is h. determine the level of the input signal from the tai out pin before a valid edge is input to the tai in pin. an interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set when the counter reaches 0000 16 (decrement count) or ffff 16 (increment count). at the same time, the contents of the reload register is transferred to the counter and the count is continued. when bit 2 is 1, each time the counter reaches 0000 16 (decrement count) or ffff 16 (increment count), the waveforms polarity is re- versed and is output from tai out pin. if bit 2 is 0, tai out pin can be used as a normal port pin. however, if bit 4 is 1 and the tai out pin is used as an output pin, the output from the pin changes the count direction. therefore, bit 4 must be 0 unless the output from the tai out pin is to be used to se- lect the count direction. fig. 23 timer ai mode register bit configuration during event counter mode fig. 24 up-down register bit configuration 76543210 1 0 0 0 1 : always ?1?in event counter mode 0 : no pulse output 1 : pulse output 0 : count at the falling edge of input signal 1 : count at the rising edge of input signal 0 : increment or decrement according to up/down flag 1 : increment or decrement according to tai out pin input signal level 0 : always ??in event counter mode : not used in event counter mode timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register addresses 56 16 57 16 58 16 59 16 5a 16 timer a0 up-down bit timer a1 up-down bit timer a2 up-down bit timer a3 up-down bit timer a4 up-down bit timer a2 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a3 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a4 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode up-down register 76543210 address 44 16
27 mitsubishi microcomputers M37753M8C-XXXFP , m37753m8c-xxxhp m37753s4cfp , m37753s4chp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer be set to 1 and bits 1, 2, 3, and 5 must be 0 . bits 6 and 7 are ig- nored. note that bits 5, 6, and 7 of the up-down register (4 4 16 ) are the two-phase pulse signal processing select bits for timers a2, a3 and a4 respectively . each timer operates in normal event counter mode when the corresponding bit is 0 and performs two-phase pulse signal processing when it is 1 . count is started by setting the count start bit to 1 . data write and read are performed in the same way as for normal event count er mode. note that the direction register of the input port mus t be set to input mode because two kinds of pulse signals, described abo ve, are input. also, there can be no pulse output in this mode. data write and data read are performed in the same way as fo r timer mode. that is, when data is written to timer ai halted, it is also written to the reload register and the counter. when data is written to timer ai which is busy , the data is written to the reload register , but not to the counter . the counter is reloaded with new data from the reload register at the next reload time. the counter can be read at any time. t wo-phase pulse processing in event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pul ses of which phases dif fer by 90 to timer a2, a3, or a4. there are two types of two-phase pulse processing operations. one uses tim ers a2 and a3, and the other uses timer a4. in both processing operations, two pulses described above are input to the t a jout (j = 2 to 4) pin and t aj in pin respectively . when timers a2 and a3 are used, as shown in figure 25, the count is incremented when a rising edge is input to the t ak in pin after the level of t ak out (k=2, 3) pin changes from l to h , and when the falling edge is input, the count is decremented. for timer a4, as shown in figure 26, when a phase-related pulse with a rising edge input to the t a4 in pin is input after the level of ta 4 out pin changes from l to h , the count is incremented at the respective rising edge and falling edge of the t a4 out pin and t a4 in pin. when a phase-related pulse with a falling edge input to the t a4 out pin is input after the level of t a4 in pin changes from h to l , the count is decremented at the respective rising edge and falli ng edge of the t a4 in pin and t a4 out pin. when performing this two-phase pulse signal processing, timer aj mode register bit 0 and bit 4 must fig. 27 timer aj mode register bit configuration when perfo rming two-phase pulse signal processing in event counter mode fig. 25 two-phase pulse processing operation of timers a2 a nd timer a3 fig. 26 two-phase pulse processing operation of timer a4 76543210 1 0 0 0 1 0 0 1 : always 01 in event counter mode 0 1 0 0 : always 0100 when processing two-phase pulse signal : not used in event counter mode timer a2 mode register timer a3 mode register timer a4 mode register addresses 58 16 59 16 5a 16 tak out tak in (k = 2, 3) increment- count increment- count increment- count decrement- count decrement- count decrement- count ta4 out ta4 in decrement-count at each edge increment-count at each edge ? ? ? ? ? y ? ? ? ? ? t ? ? ? ? ? y ? ? ? ? ? t decrement-count at each edge increment-count at each edge ? ? ? ? ? y ? ? ? ? ? t ? ? ? ? ? y ? ? ? ? ? t
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 28 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (3) one-shot pulse mode [10] figure 28 shows the bit configuration of the timer ai mode register during one-shot pulse mode. in one-shot pulse mode, bit 0 and bit 5 must be 0 and bit 1 and bit 2 must be 1. the trigger is enabled when the count start bit is 1. the trigger can be generated by software or it can be input from the tai in pin. soft- ware trigger is selected when bit 4 is 0 and the input signal from the ta i in pin is used as the trigger when it is 1. bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise of the trigger signal when it is 1. software trigger is generated by setting the bit in the one-shot start bit corresponding to each timer. figure 29 shows the bit configuration of the one-shot start register. as shown in figure 30, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7. if the contents of the counter is not 0000 16 , the tai out pin goes h when a trigger signal is received. the count direction is decrement. when the counter reaches 0001 16 , the tai out pin goes l and count is stopped. the contents of the reload register is transferred to the counter. at the same time, an interrupt request signal is gener- ated and the interrupt request bit in the timer ai interrupt control reg- ister is set. this is repeated each time a trigger signal is received. the output pulse width is if the count start flag is 0, tai out goes l. therefore, the value cor- responding to the desired pulse width must be written to timer ai before setting the timer ai count start bit. as shown in figure 31, a trigger signal can be received before the operation for the previous trigger signal is completed. in this case, the contents of the reload register is transferred to the counter by the trigger and then that value is decremented. except when retriggering while operating, the contents of the reload register is not transferred to the counter by triggering. when retriggering, there must be at least one timer count source cycle before a new trigger can be issued. data write is performed in the same way as for timer mode. when data is written in timer ai halted, it is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. undefined data is read when timer ai is read. 1 pulse frequency of the selected clock (counters value at the time of trigger). fig. 28 timer ai mode register bit configuration during one-shot pulse mode fig. 29 one-shot start register bit configuration 76543210 0 1 1 0 1 0 : always ?0?in one-shot pulse mode 1 : always ??in one-shot pulse mode 0 : software trigger 1 0 : trigger at the falling edge of tai in input 1 1 : trigger at the rising edge of tai in input 0 : always ??in one-shot pulse mode clock source select 0 0 : select pf 2 0 1 : select pf 16 1 0 : select pf 64 1 1 : select pf 512 timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register addresses 56 16 57 16 58 16 59 16 5a 16 76543210 timer a0 one-shot start bit timer a1 one-shot start bit timer a2 one-shot start bit timer a3 one-shot start bit timer a4 one-shot start bit one-shot start register address 42 16
29 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 30 pulse output example when external rising edge is selected fig. 31 example when trigger is re-issued during pulse output selected clock source pfi tai in (rising edge) tai out example when the contents of the reload register is 0003 16 selected clock source pfi tai in (rising edge) tai out example when the contents of the reload register is 0004 16
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 30 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (4) pulse width modulation mode [11] figure 32 shows the bit configuration of the timer ai mode register during pulse width modulation mode. in pulse width modulation mode, bits 0, 1, and 2 must be set to 1. bit 5 is used to determine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modulator. 16-bit length pulse width modulator is selected when bit 5 is 0 and 8-bit length pulse width modulator is selected when it is 1. the 16-bit length pulse width modulator is described first. the pulse width modulator can be started with a software trigger or with an input signal from a tai in pin (external trigger). the software trigger mode is selected when bit 4 is 0. pulse width modulator is started and a pulse is output from tai out when the timer ai start bit is set to 1. the external trigger mode is selected when bit 4 is 1. pulse width modulation starts when a trigger signal is input from the ta i in pin when the timer ai start bit is 1. whether to trigger at the fall or rise of the trigger signal is determined by bit 3. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise when it is 1. when data is written to timer ai with the pulse width modulator halted, it is written to the reload register and the counter. then when the timer ai start bit is set to 1 and a software trigger or an external trigger is issued to start modulation, the waveform shown in figure 33 is output continuously. once modulation is started, triggers are not accepted. if the value in the reload register is m, the duration h of pulse is m and the output pulse period is (2 16 C1). an interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set at each fall of the output pulse. the width of the output pulse is changed by updating timer data. the update can be performed at any time. the output pulse width is changed at the rise of the pulse after data is written to the timer. the contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. undefined data is read when timer ai is read. the 8-bit length pulse width modulator is described next. the 8-bit length pulse width modulator is selected when the timer ai mode register bit 5 is 1. the reload register and the counter are both divided into 8-bit halves. the low-order 8 bits function as a prescaler and the high-order 8 bits 1 selected clock frequency 1 selected clock frequency function as the 8-bit length pulse width modulator. the prescaler counts the clock selected by bits 6 and 7. a pulse is generated when the counter reaches 0000 16 as shown in figure 34. at the same time, the contents of the reload register is transferred to the counter and count is continued. fig. 32 timer ai mode register bit configuration during pulse width modulation mode 76543210 1 1 1 1 1 : always ?1?in pulse width modulation mode 1 : always ??in pulse width modulation mode 0 : software trigger 1 0 : trigger at the falling of tai in input 1 1 : trigger at the rising of tai in input 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator clock source select bit 0 0 : select pf 2 0 1 : select pf 16 1 0 : select pf 64 1 1 : select pf 512 timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register addresses 56 16 57 16 58 16 59 16 5a 16
31 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer high-order 8 bits of the reload register are m, the duration h of pulse is and the output pulse period is 1 selected clock frequency therefore, if the low-order 8 bits of the reload register are n, the pe- riod of the generated pulse is (n+1). the high-order 8 bits function as an 8-bit length pulse width modula- tor using this pulse as input. the operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. if the 1 selected clock frequency 1 selected clock frequency fig. 33 16-bit length pulse width modulator output pulse example fig. 34 8-bit length pulse width modulator output pulse example selected clock source pfi tai in (rising edge) tai out 1/pfi (2 16 ?1) 1/pfi (m) this trigger is not accepted example when the contents of the reload register is 0003 16 selected clock source pfi tai in (falling edge) prescaler output (when n = 2) 8-bit length pulse width modulator output (when m = 2) 1/pfi (n + 1) (2 8 ?1) 1/pfi (n + 1) (m) 1/pfi (n + 1) (n+1) m. (n+1) (2 8 C1).
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 32 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer timer b figure 35 shows a block diagram of timer b. timer b has three modes: timer mode, event counter mode, and pulse period measurement/pulse width measurement mode. the mode is selected with bits 0 and 1 of the timer bi mode register (i=0 to 2). each of these modes is described below. (1) timer mode [00] figure 36 shows the bit configuration of the timer bi mode register during timer mode. bits 0 and 1 of the timer bi mode register must always be 0 in timer mode. bits 6 and 7 are used to select the clock source. the counting of the selected clock starts when the count start bit is 1 and stops when 0. as shown in figure 19, the timer bi count start bit is at the same ad- dress as the timer ai count start bit. the count is decremented, an interrupt occurs, and the interrupt request bit in the timer bi interrupt control register is set when the contents becomes 0000 16 . at the same time, the contents of the reload register is stored in the counter and count is continued. timer bi does not have a pulse output function or a gate function like timer a. when data is written to timer bi halted, it is written to the reload reg- ister and the counter. when data is written to timer bi which is busy, the data is written to the reload register, but not to the counter. the new data is reloaded from the reload register to the counter at the next reload time and counting continues. the contents of the counter can be read at any time. fig. 35 timer b block diagram data bus (odd) data bus (even) reload register (16) counter (16) count start bit event counter note: perform write and read to/from timer bi register in the condition of 16-bit data length : data length flag (m) =?? (40 16 ) counter reset circuit addresses timer b0 51 16 50 16 timer b1 53 16 52 16 timer b2 55 16 54 16 ?timer ?pulse period measurement/pulse width measurement clock source selection pf 2 pf 16 pf 64 pf 512 tbi in (i = 0 ?2) polarity selection and edge pulse generator (lower 8 bits) (higher 8 bits)
33 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (2) event counter mode [01] figure 37 shows the bit configuration of the timer bi mode register during event counter mode. in event counter mode, bit 0 in the timer bi mode register must be 1 and bit 1 must be 0. the input signal from the tbi in pin is counted when the count start flag is 1 and counting is stopped when it is 0. count is performed at the fall of the input signal when bits 2, and 3 are 0 and at the rise of the input signal when bit 3 is 0 and bit 2 is 1. when bit 3 is 1 and bit 2 is 0, count is performed at the rise and fall of the input signal. data write, data read and timer interrupt are performed in the same way as for timer mode. (3) pulse period measurement/pulse width measurement mode [10] figure 38 shows the bit configuration of the timer bi mode register during pulse period measurement/pulse width measurement mode. in pulse period measurement/pulse width measurement mode, bit 0 must be 0 and bit 1 must be 1. bits 6 and 7 are used to select the clock source. the selected clock is counted when the count start flag is 1 and counting stops when it is 0. the pulse period measurement mode is selected when bit 3 is 0. in pulse period measurement mode, the selected clock is counted dur- ing the interval starting at the fall of the input signal from the tbi in pin to the next fall or at the rise of the input signal to the next rise; the result is stored in the reload register. in this case, the reload register acts as a buffer register. when bit 2 is 0, the clock is counted from the fall of the input signal to the next fall. when bit 2 is 1, the clock is counted from the rise of the input signal to the next rise. in the case of counting from the fall of the input signal to the next fall, counting is performed as follows. as shown in figure 39, when the fall of the input signal from tbi in pin is detected, the contents of the counter is transferred to the reload register. next the counter is cleared and count is started from the next clock. when the fall of the next input signal is detected, the contents of the counter is trans- ferred to the reload register once more, the counter is cleared, and the count is started. the period from the fall of the input signal to the next fall is measured in this way. after the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt request bit in the timer bi interrupt control register is set. however, no interrupt request signal is generated when the contents of the counter is transferred first to the reload register after the count start bit is set to 1. when bit 3 is 1, the pulse width measurement mode is selected. pulse width measurement mode is the same as the pulse period measurement mode except that the clock is counted from the fall of the tbi in pin input signal to the next rise or from the rise of the input signal to the next fall as shown in figure 40. fig. 36 timer bi mode register bit configuration during timer mode fig. 37 timer bi mode register bit configuration during event counter mode fig. 38 timer bi mode register bit configuration during pulse period measurement/pulse width measurement mode 0 0 : always ?0?in timer mode : not used in timer mode and may be any not used in timer mode clock source select bit 0 0 : select pf 2 0 1 : select pf 16 1 0 : select pf 64 1 1 : select pf 512 76543210 0 0 timer b0 mode register timer b1 mode register timer b2 mode register addresses 5b 16 5c 16 5d 16 0 1 : always ?1?in event counter mode 0 0 : count at the falling edge of input signal 0 1 : count at the rising edge of input signal 1 0 : count at the both falling edge and rising edge of input signal : not used in event counter mode 76543210 1 0 timer b0 mode register timer b1 mode register timer b2 mode register addresses 5b 16 5c 16 5d 16 1 0 : always ?0?in pulse period measurement/pulse width measurement mode 0 0 : count from the falling edge of input signal to the next falling one 0 1 : count from the rising edge of input signal to the next rising one 1 0 : count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one timer bi overflow flag clock source select bit 0 0 : select pf 2 0 1 : select pf 16 1 0 : select pf 64 1 1 : select pf 512 76543210 0 1 timer b0 mode register timer b1 mode register timer b2 mode register addresses 5b 16 5c 16 5d 16
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 34 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer when timer bi is read, the contents of the reload register is read. note that in this mode, the interval between the fall of the tbi in pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. timer bi overflow flag which is bit 5 of timer bi mode register is set to 1 when the timer bi counter reaches 0000 16 , which indicates that a pulse width or pulse period is longer than that which can be mea- sured by a 16-bit length. this flag is cleared by writing data to the corresponding timer bi mode register. this bit is set to 1at reset. fig. 39 pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one) fig. 40 pulse width measurement mode operation selected clock source pfi tbi in reload register ? counter counter ? 0 count start flag interrupt request signal selected clock source pfi tbi in reload register ? counter counter ? 0 count start flag interrupt request signal
35 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer timer function for motor control three-phase motor drive waveform and pulse motor drive waveform can be output by using plural internal timers a and b. those modes are explained bellow. three-phase motor drive waveform output mode (three-phase waveform mode) three-phase waveform mode using four timers of the timers a0, a1, a2 and b4 is selected by setting the waveform output select bits of the waveform output mode register (address 1a 16 , figure 41) to 100 2 . there are two types of the three-phase waveform mode: three- phase mode 0 and three-phase mode 1. bit 4 of the waveform out- put mode register selects either mode. in three-phase waveform mode, set the corresponding timer mode registers of timers a0, a1, and a2 to select the one-shot pulse mode with the rising edge of ex- ternal trigger; set the timer mode register of timer b2 to select the timer mode. figure 43 shows the three-phase waveform mode block diagram. the three-phase waveform mode outputs six waveforms, positive waveforms (u, v, w phases) and negative waveforms (u, v, w phases), from the respective ports with l level active. timer a2 controls u and u phases; timer a1 does v and v phases and timer a0 does w and w phases. timer b2 controls those one- shot pulses period of timers a2, a1 and a0. in the waveform output, a short circuit prevention time can be set to prevent l level of positive waveforms (u, v, w phases) from over- lapping with l level of their negative waveforms (u, v, w phases). the short circuit prevention time can be set with three 8-bit dead- time timers, sharing one reload register. the dead-time timer oper- ates as a one-shot timer. as its start trigger, both the rising and falling edges of timers a0 to a2s one-shot pulses or their falling edge. bit 6 of the waveform output mode register selects it. when that is 0, both the rising and falling edges become the start trigger; when that is 1, the falling edge becomes it. timer a0 mode register 56 16 timer a1 mode register 57 16 timer a2 mode register 58 16 fix to ?0?in three-phase waveform mode fix to ?111?in three-phase waveform mode clock source select bit 0 0 : select pf 2 0 1 : select pf 16 1 0 : select pf 64 1 1 : select pf 512 76543210 0 1 11 0 address timer b2 mode register 5d 16 fix to ?0?in three-phase waveform mode not used in three-phase waveform mode clock source select bit 0 0 : select pf 2 0 1 : select pf 16 1 0 : select pf 64 1 1 : select pf 512 76543210 0 0 address 1 fig. 42 timer a0, a1, a2, mode register and timer b2 mode regis- ter bit configuration waveform output mode register 1a 16 waveform output select bits 100 : fix to ?00?in three-phase waveform mode (valid in three-phase mode 1) three-phase output polarity set buffer 0 : ??output 1 : ??output three-phase mode select bit 0 : three-phase mode 0 1 : three-phase mode 1 not used in three-phase waveform mode dead-time timer trigger select bit 0 : both edge of one-shot pulse with timers a2 to a0 1 : only the falling edge of one-shot pulse with timers a2 to a0 waveform output control bit 0 : waveform output disabled 1 : waveform output enabled 76543210 0 0 1 address note : only when bit 5 of the particular function select register 1 (in fig. 15) is set to ?? this register? contents can be changed from the status during reset (in fig.76). fig. 41 waveform output mode register bit configuration
mitsubishi microcomputers M37753M8C-XXXFP , m37753m8c-xxxhp m37753s4cfp , m37753s4chp 36 preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 43 three-phase waveform mode block diagram timer b2 timer a2 reload interval control reload register t t s s t t dq dq dq dq r dq r dq tr dq t dq t dq t dq t dq t dq t dq r dq r qd r dq tr dq r dq tr dq r dq tr dq r dq tr dq r dq tr dq r dq tr q s r q t q s r q t q s r q t waveform output control bit reset interrupt request interval set bit timer b2 interrupt request signal in t 0 u v w u v w (timer mode) three-phase output polarity set buffer interrupt validity output select bit dead-time timer clock source select bit pf 2 pf 8 pf 4 timer a2 1 timer a2 counter (one-shot pulse mode) 0 1 u-phase output polarity set buffer timer a0 reload timer a0 1 timer a0 counter (one-shot pulse mode) w-phase output polarity set buffer 0 1 reset 0 1 three-phase mode select bit reset reset timer a1 reload timer a1 counter v-phase output polarity set buffer timer a1 1 0 1 output polarity set toggle flip- flop 2 dead-time timer (8) dead-time timer (8) output polarity set toggle flip- flop 1 dead-time timer (8) output polarity set toggle flip- flop 0 h output of w-phase fix buffer h output of w-phase fix buffer h output of v-phase fix buffer h output of v-phase fix buffer h output of u-phase fix buffer h output of u-phase fix buffer note : only when bit 5 of the particular function select register 1 (in fig. 15) is set to 1 , the following registers contents can be changed from the status after reset (in fig.76): waveform output mode register (address 1a 16 ), dead-time timer (address 1b 16 ), pulse output data registers 0 and 1 (addresses 1c 16 , 1d 16 ), and timer a write register (address 45 16 ). (one-shot pulse mode)
37 mitsubishi microcomputers M37753M8C-XXXFP , m37753m8c-xxxhp m37753s4cfp , m37753s4chp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer when writing data to the dead-time timer (address 1b 16 ), the data is written to the reload register shared by three dead-time tim ers. when the dead-time timers catch the start trigger from the r espec- tive timers, the reload register contents are transferred to its counter and the dead-time timer decrements with the clock source sel ected by bits 6 and 7 of pulse output data register (address 1c 16 ). addition- ally , this timer can accept another trigger before completion of the preceding trigger operation. in this case, after transferrin g the reload register contents to the dead-time timer at acceptance of th e trigger , the value is decremented. the dead-time timer operates as a one-shot timer . accordingly , this timer starts pulse output when the trigger is caught, and fi nishes pulse output and stops operation when its contents become 00 16 , and waits next trigger. pulse output data register 1 1c 16 v-phase output polarity set buffer (three-phase mode 0) 0 : h output 1 : l output interrupt request interval set bit (three-phase mode 1) 0 : at every second time 1 : at every fourth time u-phase output polarity set buffer (three-phase mode 0) 0 : h output 1 : l output interrupt validity output select bit (three-phase mode 1) 0 : timer b2 interrupt request generated at each even-numbered underflow of timer b2. 1 : timer b2 interrupt request generated at each odd-numbered underflow of timer b2. 5 : not used in three-phase waveform mode h output of w-phase fix buffer 0 : released from fixed output 1 : h output fixed h output of v-phase fix buffer 0 : released from fixed output 1 : h output fixed h output of u-phase fix buffer 0 : released from fixed output 1 : h output fixed clock-source-of-dead-time timer select bit 00 : pf 2 selected 01 : pf 4 selected 10 : pf 8 selected 11 : do not select. 76543210 address pulse output data register 0 1d 16 5 : not used in three-phase waveform mode (valid in three-phase mode 0) w-phase output polarity set buffer 0 : h output 1 : l output h output of w-phase fix buffer 0 : released from fixed output 1 : h output fixed h output of v-phase fix buffer 0 : released from fixed output 1 : h output fixed h output of u-phase fix buffer 0 : released from fixed output 1 : h output fixed 76543210 address note : only when bit 5 of the particular function select register 1 (in fig. 15) is set to 1 , these registers contents can be changed from the status during reset (in fig.76). fig. 44 bit configuration of pulse output data registers 1 and 0 in three-phase waveform mode in the three-phase waveform mode, setting bit 7 of the wavef orm out- put mode register (address 1a 16 ) to 1 makes positive waveforms (u, v , w phases) and their negative waveforms (u, v , w phases) out- put from the respective ports. when that bit is 0 , their ports are floating. that bit is cleared to 0 by inputting falling edge to the int 0 pin or reset other than clearing by an instruction.. additionally , setting bits 5 to 3 of the pulse output data register 1 (a d- dress 1c 16 ) to 1 makes the corresponding positive waveforms fixed to h , and setting bits 7 to 5 of the pulse output data register 0 (address 1d 16 ) to 1 makes the corresponding negative waveforms fixed to h . when selecting the three-phase waveform mode, int 0 pin become input-only pin.
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 38 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer three-phase mode 0 in selecting three-phase waveform mode, three-phase mode 0 is se- lected by setting bit 4 of the waveform output mode register (address 1a 16 ) to 0. the output polarity of three-phase waveform depends on the output polarity set toggle flip-flop. the positive waveform of the three-phase waveform is h output when the toggle flip-flop is 0; it is l output when the toggle flip-flop is 1. (three-phase waveform is output as a negative waveform.) each output polarity set toggle flip-flop has the output polarity set buffer shown in figure 44. when the timer b2s counter contents be- come 0000 16 , the contents of output polarity set buffer are set into the output polarity set toggle flip-flop. after that, the polarity of the contents of output polarity set toggle flip-flop are reversed each time completion of one-shot pulse of timer (timers a2 to a0) correspond- ing to each phase. figure 45 shows an example of u-phase waveform and the output operation is explained. three-phase mode 0 becomes valid when writing 0 to the u-phase output polarity set buffer (bit 1 at address 1c 16 ) and actuating the timer b2. when the counter of timer b2 be- comes 0000 16 , the timer b2 interrupt request signal occurs and the timer a2 simultaneously starts one-shot pulse output. at this time, the contents of u-phase output polarity set buffer, 0 in this case, are set into the output polarity set toggle flip-flop 2. when the one-shot pulse output of timer a2 is completed, the con- tents of output polarity set toggle flip-flop 2 is reversed from 0 to 1. simultaneously, the one-shot pulse of the 8-bit dead-time timer is output for ensuring time not to overlap l levels of u phase wave- form and its negative u phase waveform. the u-phase waveform output keeps h level from the start until the one-shot pulse output of the dead-time timer is completed, even if the contents of output polarity set toggle flip-flop 2 are reversed from 0 to 1 owing to the timer a2s one-shot pulse output. when the one-shot pulse output of the dead-time timer is completed, 1 of output polarity set toggle flip-flop 2 which has been reversed be- comes valid and the u phase waveform changes to l level. signal output each time timer b2 becomes 0000 16 one-shot pulse output with timer a2 contents of output polarity set toggle flip-flop 2 reversed pulse output signal with dead-time timer u-phase waveform output u-phase waveform output then, write 1 to the u-phase output polarity set buffer (bit 1 at ad- dress 1c 16 ) before the counter of timer b2 becomes 0000 16 . after that, when the counter of timer b2 becomes 0000 16 , the timer a2 starts one-shot pulse output. simultaneously, the contents of u- phase output polarity set buffer, 1 in this case, are set into the out- put polarity set toggle flip-flop 2 and the u phase waveform remains l level. when the one-shot pulse output of timer a2 is completed, the con- tents of output polarity set toggle flip-flop 2 is reversed from 1 to 0. simultaneously, the one-shot pulse output of the dead-time timer starts. when the contents of output polarity set toggle flip-flop 2 are re- versed from 1 to 0, the u-phase waveform changes its output level from l to h without waiting for completion of the one-shot pulse output of the dead-time timer. u-phase waveform is generated by repeating the operation above. the way to generate u-phase waveform, which is the negative phase of u-phase, is the same as that for u-phase waveform except that the contents of output polarity set toggle flip-flop 2 are treated as the reversed signal from the case of u-phase waveform. in this way, u-phase waveform and u-phase waveform, having the negative phase of u-phase, are output from the pins so that their l levels do not overlap each other. the width of l level can be also modified by changing the value of timer b2 or timer a2. v-, w-phase waveform and v-, w-phase waveform, having their negative phase, are similarly output according to the corresponding timer operation. the explanation above is an example of three-phase waveform gen- erating due to an triangular wave modulation. three-phase waveform due to a saw-tooth-wave modulation can also be generated by fixing each beginning level of phases. fig. 45 u-phase waveform output example in three-phase mode 0 (triangular wave modulation)
39 mitsubishi microcomputers M37753M8C-XXXFP , m37753m8c-xxxhp m37753s4cfp , m37753s4chp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer three-phase mode 1 in selecting three-phase waveform mode, three-phase mode 1 i s selected by setting bit 4 of the waveform output mode regist er (ad- dress 1a 16 ) to 1 . in this mode, each of timers a0 to a2 can have two timer registers and the contents of those registers are alternately reloaded into the counter each time the counter of timer b2 becomes 0000 16 . about write operation to two timer registers, when rewriting to ea ch timer register of timers a0, a1 and a2 after writing to each timer register of them, the data is written each to timers a0 1 , a1 1 and a2 1 . when writ- ing to each timer register , the timer a write register (in figure 46) in- dicates the timer to be intended for write. the interrupt request normally occurs when the counter of ti mer b2 becomes 0000 16 . however , this occurrence interval can be switched between every second time and every fourth time. bit 0 of the pulse output data register 1 (address 1c 16 ) selects that. additionally , 0 or 1 of the three-phase output polarity set buf fer can be used as the occurrence factor of timer b2 interrupt r equest. bit 1 of the pulse output data register 1 (address 1c 16 ) selects that. when the timer b2 s counter contents become 0000 16 , the contents of three-phase output polarity set buf fer are set into the output polar- ity set toggle flip-flop on which .the output polarity of th ree-phase waveform depends. the contents of three-phase output polarity set buf fer are reversed after that operation. the polarity of the contents of output polarity set toggle f lip-flop is re- versed each time completion of one-shot pulse of timer (time rs a2 to a0) corresponding to each phase. figure 47 shows an example of u-phase waveform and the outpu t operation is explained. w rite 0 to the three-phase output polarity set buffer (bit 3 at ad- dress 1a 16 ). clear the interrupt request interval set bit (bit 0 at ad - dress 1c 16 ) to 0 so that the timer b2 interrupt request may occur at every second time. additionally , clear the interrupt validity output se- lect bit (bit 1 at address 1c 16 ) so that the timer b2 interrupt request may occur at 0 of the three-phase output polarity set buf fer . after the procedure above, three-phase mode 1 starts operati on when actuating the timer b2. when the counter of timer b2 becomes 0000 16 , the timer b2 inter- rupt request occurs and timer a2 simultaneously starts one-shot pulse output. at this time, the contents of three-phase output polarity set buf fer , 0 in this case, are set into the output polarity set toggle flip-flop 2. the contents of three-phase output polarity set buffer are reversed from 0 to 1 after that operation. when the timer a2 counter counts the value written into the timer a2 and the one-shot pulse output of timer a2 is completed, the contents of output polarity set toggle flip-flop 2 are reversed from 0 to 1 . si- multaneously , the one-shot pulse of the 8-bit dead-time timer is out- __ put for ensuring time, so that l levels of u- and u-phase waveforms do not overlap. timer b2 interrupt request signal signal output each time timer b2 becomes 0000 16 one-shot pulse output with timer a2 timer a2 timer a2 1 contents of output polarity set toggle flip-flop 2 reversed pulse output signal with dead-time timer u-phase waveform output u-phase waveform output n1 n1 n3 n5 n7 n2 n4 n6 n8 n2 n3 n4 n5 n6 address timer a write register 45 16 timer a0 write bit 0 : write to timer a0 1 : write to timer a0 1 timer a1 write bit 0 : write to timer a1 1 : write to timer a1 1 timer a2 write bit 0 : write to timer a2 1 : write to timer a2 1 76543210 note: only when bit 5 of the particular function select register 1 (in fig. 15) is set to 1 , this register s contents can be changed from the status after reset (in fig.76). fig. 47 u-phase waveform output example in three-phase mode 1 (triangular wave modulation) fig. 46 timer a write flag bit configuration
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 40 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer the u-phase waveform output keeps h level from the start until the one-shot pulse output of the dead-time timer is completed, even if the contents of output polarity set toggle flip-flop 2 are reversed from 0 to 1 owing to the timer a2s one-shot pulse output. when the one-shot pulse output of the dead-time timer is completed, 1 of output polarity set toggle flip-flop 2 which has been reversed becomes valid and the u-phase waveform changes to l level. then, when the counter of timer b2 becomes 0000 16 , the timer a2 counter counts the value written into timer a2 and timer a2 starts one-shot pulse output. simultaneously, the contents of three-phase output polarity set buffer are set into the output polarity set toggle flip-flop 2. however, the u-phase waveform remains l level, be- cause the value is the same (1). the contents of three-phase output polarity set buffer are reversed from 1 to 0 after that operation. when the one-shot pulse output of timer a2 is completed, the con- tents of output polarity set toggle flip-flop 2 is reversed from 1 to 0. simultaneously, the one-shot pulse output of the dead-time timer starts. when the contents of output polarity set toggle flip-flop 2 is reversed from 1 to 0, the u-phase waveform changes its output level from l to h without waiting for completion of the one-shot pulse output of the dead-time timer. u-phase waveform is generated by repeating the operation above. the way to generate u-phase waveform, which is the negative phase of u-phase, is the same as that for u-phase waveform except that the contents of output polarity set toggle flip-flop 2 is treated as the reversed signal from the case of u-phase waveform. in this way, u-phase waveform and u-phase waveform, having the negative phase of u-phase, are output from the pins so that their l levels do not overlap each other. the width of l level can be also modified by changing the value of timer b2, timer a2 or timer a2 1 . v-, w-phase waveform and v-, w-phase waveform, having their negative phase, are similarly output according to the corresponding timer operation.
41 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer pulse output port mode figure 48 shows the pulse output port mode block diagram. this mode has an 8-bit pulse output port. the waveform output se- lect bits (bits 0 to 2) of waveform output mode register (address 1a 16 , figure 49) select use of pulse output port. the 8-bit pulse out- put port is divided into 4 bits and 4 bits, or 6 bits and 2 bits with the pulse output mode select bit (bit 4) of pulse output data register 1 (address 1c 16 , figure 51) ; each of them can be individually con- trolled. d r q d r q d q t t t dq dq dq dq dq dq dq t dq dq dq d15 d14 d13 d3 d2 d1 d0 d11 d10 d9 d8 timer a0 timer a1 rtp1 3 rtp1 2 rtp1 1 rtp1 0 rtp0 3 rtp0 2 rtp0 1 rtp0 0 waveform output control bit 0 polarity select bit reset pulse width modulation select bit 0 reset pulse output mode select bit pulse width modulation data bit data bus (even) data bus (odd) pulse width modulation output of timer a4 pulse width modulation output of timer a3 pulse width modulation output of timer a2 pulse width modulation select bit 1 pulse output data register 1 pulse output data register 0 waveform output control bit 0 note : only when bit 5 of the particular function select register 1 (in fig. 15) is set to 1, the following registers contents can be changed from the status after reset (in fig.76) : waveform output mode register (address 1a 16 ) and pulse output data registers 0 and 1 (addresses 1c 16 , 1d 16 ). fig. 48 pulse output port mode block diagram set timers a1 and a0 to the timer mode because they are used in the pulse output mode. additionally, set bit 2 of the corresponding timer ai mode register to 1 to use a pulse output port because the pulse output port is multiplexed with the tai out (i = 0 to 4). figure 50 shows the bit configuration of timer a1 and a0 mode registers in the pulse output port mode. timers a1 and a0 start count when setting the corresponding timer count start flag to 1, and they stop it when clearing that flag to 0.
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 42 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer pulse mode 0 this mode divides a pulse output port into 4 bits and 4 bits and indi- vidually controls them. when setting the pulse output mode select bit to 0, and setting bits 2 and 1 to 0 and bit 0 to 1 of the waveform output select bits, four of rtp1 3 , rtp1 2 , rtp1 1 , and rtp1 0 become the pulse output ports with rtp1 selected. when setting the pulse output mode select bit to 0, and setting bits 2 and 0 to 0 and bit 1 to 1 of the waveform output select bits, four of rtp0 3 , rtp0 2 , rtp0 1 , rtp0 0 become the pulse output ports with rtp0 selected. when setting the pulse output mode select bit to 0, and setting bit 2 to 0 and bits 1 and 0 to 1 of the waveform output select bits, the following two groups become the pulse output ports with rtp1 and rtp0 selected: ?four of rtp1 3 , rtp1 2 , rtp1 1 , rtp1 0 ?four of rtp0 3 , rtp0 2 , rtp0 1 , rtp0 0 . each time the contents of timer a1 counter become 0000 16 , the contents of pulse output data register 1 (low-order 4 bits at address 1c 16 ) corresponding to rtp1 3 , rtp1 2 , rtp1 1 , rtp1 0 are output from ports. each time the contents of timer a0 counter become 0000 16 , the contents of pulse output data register 0 (low-order 4 bits at address 1d 16 ) corresponding to rtp0 3 , rtp0 2 , rtp0 1 , rtp0 0 are output from ports. when writing 0 to the specified bit of pulse output data register, l level is output from the pulse output port when the contents of cor- responding timer counter become 0000 16 ; when writing 1 to it, h level is output from the pulse output port. note : only when bit 5 of the particular function select register 1 (in fig. 15) is set to 1, this registers contents can be changed from the status after reset (in fig.76). waveform output mode register 1a 16 waveform output select bits 000 : parallel port 001 : rtp1 selected (valid in pulse mode 0) 010 : rtp0 selected (valid in pulse mode 0) 011 : in pulse mode 0 rtp1 and rtp0 selected in pulse mode 1 rtp1, rtp0 3 , rtp0 2 , rtp0 1 , rtp0 0 selected polarity select bit (valid for rtp0 in pulse mode 0) 0 : positive polarity 1 : negative polarity pulse width modulation select bit 0 (valid for rtp1 in pulse mode 0; valid for rtp1, rtp0 3 , rtp0 2 in pulse mode 1) 0 : no modulation by timer a2 1 : modulation by timer a2 pulse width modulation select bit 1 (valid in pulse mode 1) 0 : modulation by timer a2 1 : modulation for rtp0 3 , rtp0 2 by timer a2 modulation for rtp1 1 , rtp1 0 by timer a3 modulation for rtp1 3 , rtp1 2 by timer a4 when selecting pulse mode 0, fix this bit to 0. waveform output control bit 0 0 : in pulse mode 0 disable rtp0 waveform output in pulse mode 1 disable rtp0 1 , rtp0 0 waveform output 1 : in pulse mode 0 enable rtp0 waveform output in pulse mode 1 enable rtp0 1 , rtp0 0 waveform output waveform output control bit 1 0 : in pulse mode 0 disable rtp1 waveform output in pulse mode 1 disable rtp1, rtp0 3 , rtp0 2 waveform output 1 : in pulse mode 0 enable rtp1 waveform output in pulse mode 1 enable rtp1, rtp0 3 , rtp0 2 waveform output 76543210 address timer a0 mode register 56 16 timer a1 mode register 57 16 100 : fix to 100 in pulse output port mode 5 : not used in pulse output port mode 00 : fix to 00 in pulse output port mode clock source select bit 00 : pf 2 selected 01 : pf 16 selected 10 : pf 64 selected 11 : pf 512 selected 76543210 0 0 1 0 0 address fig. 49 bit configuration of waveform output mode register in pulse output port mode fig. 50 bit configuration of timer a1 and a0 mode registers in pulse output port mode h h
43 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer additionally, pulse width modulation can be applied for the pulse out- put port rtp1. because the timer a2 is used for pulse width modula- tion, actuate timer a2 in the pulse width modulation mode. when any bit of pulse output data is 1, the pulse to which pulse width modula- tion is applied is output from the pulse output port when the contents of timer a1 counter become 0000 16 . pulse width modulation by timer a2 is applied when setting the pulse width modulation select bit 0 (bit 4) of waveform output mode regis- ter to 1, pulse width modulation select bit 1 (bit 5) to 0, and the pulse width modulation data bit of rtp1 (bit 5) of pulse output data register 0 to 1. rtp0 3 , rtp0 2 , rtp0 1 and rtp0 0 can output the contents of pulse output data register 0 by setting the polarity select bit (bit 3) of wave- form output mode register. when the polarity select bit is 1, the re- versed contents of pulse output data register 0 is output; when that bit is 0, the contents of pulse output data register 0 are output as it is. figure 52 shows example waveforms in the pulse mode 0. in ports selecting the pulse mode 0, output of rtp0 3 , rtp0 2 , rtp0 1 and rtp0 0 is controlled by the waveform output control bit 0 (bit 6) of waveform output mode register; output of rtp1 3 , rtp1 2 , rtp1 1 and rtp1 0 is done by the waveform output control bit 1 (bit 7). when setting the waveform output control bit to 1, waveform is out- put from the corresponding port. when clearing that bit to 0, wave- form output from the corresponding port stops, and the port becomes floating. the waveform output control bits are cleared to 0 by reset other than clearing with instructions. pulse mode 1 this mode divides a pulse output port into 6 bits and 2 bits, and indi- vidually controls them. when setting the pulse output mode select bit to 1, and setting bit 2 to 0 and bits 1 and 0 to 1 of the waveform output select bits, the following two groups become the pulse output ports: ?six of rtp1 3 , rtp1 2 , rtp1 1 , rtp1 0 , rtp0 3 , rtp0 2 ?two of rtp0 1 , rtp0 0 . timer a1 controls six of rtp1 3 , rtp1 2 , rtp1 1 , rtp1 0 , rtp0 3 , and rtp0 2 ; timer a0 controls two of rtp0 1 , rtp0 0 . additionally, pulse width modulation can be applied for the pulse out- put ports (rtp1, rtp0 3 , rtp0 2 ). the pulse width modulation select bit 1 (bit 5) of waveform output mode register selects the type of modulation: the common modulation to six of rtp1 3 , rtp1 2 , rtp1 1 , rtp1 0 , rtp0 3 and rtp0 2 or the modulation to every two ports of rtp1 3 and rtp1 2 , rtp1 1 and rtp1 0 , rtp0 3 and rtp0 2 . when setting that bit to 0, the common modulation to six ports is applied; when setting that bit to 1, the modulation to every two ports is applied. the timer a2 is used for the common modulation to six ports; the timers a2, a3 and a4 are used for the modulation to every two ports. accordingly, actuate the respective timers in the pulse width modulation mode. when any bit of pulse output data is 1, the pulse to which pulse width modulation is applied is output from the pulse output port when the contents of timer a1 counter become 0000 16 . pulse width modulation by corresponding timers is applied when set- ting the pulse width modulation select bit 0 of waveform output mode register to 1 and the corresponding pulse width modulation data bits (bits 7 to 5) of pulse output data register 0 to 1. the polarity select bit (bit 3) of waveform output mode register must be 0 to select the positive polarity. the other operations are the same as that of pulse mode 0. figure 53 shows example waveforms in the pulse mode 1. in ports selecting the pulse mode 1, output of rtp0 1 and rtp0 0 is controlled by the waveform output control bit 0 (bit 6) of waveform output mode register; output of rtp1 3 , rtp1 2 , rtp1 1 , rtp1 0 , rtp0 3 and rtp0 2 is done by the waveform output control bit 1 (bit 7). when setting the waveform output control bit to 1, waveform is out- put from the corresponding port. when clearing that bit to 0, wave- form output from the corresponding port stops and the port becomes floating. the waveform output control bits are cleared to 0 by reset other than clearing with instructions. pulse output data register 1 1c pulse output mode select bit 16 rtp1 0 pulse output data bit rtp1 1 pulse output data bit rtp1 2 pulse output data bit rtp1 3 pulse output data bit 0 : pulse mode 0 1 : pulse mode 1 : not used in pulse output port mode 76543210 address pulse output data register 0 1d 16 rtp0 0 pulse output data bit rtp0 1 pulse output data bit rtp0 2 pulse output data bit rtp0 3 pulse output data bit in pulse mode 0 pulse width modulation data bit of rtp1 in pulse mode 1 pulse width modulation data bit of rtp0 3 , rtp0 2 in pulse mode 1 pulse width modulation data bit of rtp1 1 , rtp1 0 in pulse mode 1 pulse width modulation data bit of rtp1 3 , rtp1 2 76543210 address note : only when bit 5 of the particular function select register 1 (in fig. 15) is set to 1, this registers contents can be changed from the status after reset (in fig.76). fig. 51 bit configuration of pulse output data registers 1 and 0 in pulse output port mode
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 44 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 52 example waveforms in pulse mode 0 fig. 53 example waveforms in pulse mode 1 pulse outpu port (rtp1) example rtp1 3 rtp1 2 rtp1 0 rtp1 1 rtp1 3 rtp1 2 rtp1 0 rtp1 1 rtp0 3 rtp0 2 rtp0 0 rtp0 1 signal output each time timer a1 becomes 0000 16 example of pulse width modulation for above pulse output port using timer a2 pulse outpu port (rtp0) example in the case of polarity select bit = ?? signal output each time timer a1 becomes 0000 16 signal output each time timer a0 becomes 0000 16 rtp1 3 rtp0 3 rtp1 2 rtp0 2 rtp1 0 rtp1 1 rtp1 3 rtp0 3 rtp1 2 rtp0 2 rtp1 0 rtp1 1 pulse outpu port (6 bits) example signal output each time timer a1 becomes 0000 16 example of pulse width modulation for above pulse output port using timer a2 signal output each time timer a1 becomes 0000 16
45 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer serial i/o ports two independent serial i/o ports are provided. figure 54 shows a block diagram of the serial i/o ports. bits 0, 1, and 2 of the uarti(i = 0,1) transmit/receive mode register shown in figure 55 are used to determine whether to use port p8 as parallel port, clock synchronous serial i/o port, or asynchronous (uart) serial i/o port using start and stop bits. figures 56 and 57 show the connections of receiver/transmitter ac- cording to the mode. figure 58 shows the bit configuration of the uarti transmit/receive control register. each communication method is described below. fig. 55 uarti transmit/receive mode register bit configuration fig. 54 serial i/o port block diagram data bus(odd) data bus(even) data bus (odd) data bus(even) bit converter receive register t x d i r x d i receive control circuit transmission control circuit transmit register bit converter 1/16 divider 1/2 divider 1/(n + 1) divider 1/16 divider receive clock transmission clock transmit buffer register uart transmission clock synchronous clock synchronous clock synchronous (internal clock) external clock source selection uart0(31 16 ) uart1(39 16 ) internal pf 2 pf 16 pf 64 pf 512 clock synchronous (internal clock) clock synchronous (external clock) uart receive d 7 d 6 d 5 d 4 d 3 d 2 d 1 receive buffer register d 0 d 7 d 8 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0d 8 0 0 0 0 0 0 bit rate generator uart0(33 16 ,32 16 ) uart1(3b 16 ,3a 16 ) uart0(37 16 ,36 16 ) uart1(3f 16 ,3e 16 ) cts i /rts i clk i serial i/o mode select bit 0 0 0 : parallel port 0 0 1 : clock synchronous 1 0 0 : 7-bit uart 1 0 1 : 8-bit uart 1 1 0 : 9-bit uart internal/external clock select bit 0 : internal clock 1 : external clock stop bit length select bit 0 : 1 stop bit 1 : 2 stop bits even/odd parity select bit 0 : odd parity 1 : even parity parity enable select bit 0 : no parity 1 : with parity sleep select bit 0 : no sleep 1 : sleep 76543210 uart 0 transmit/receive mode register uart 1 transmit/receive mode register addresses 30 16 38 16
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 46 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 56 receiver block diagram fig. 57 transmitter block diagram fig. 58 uarti transmit/receive control register bit configuration data bus(odd) data bus(even) bit converter d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 stop bit stop bit parity bit no parity receive register r x d i receive buffer register 9 bit 7 bit 7bit 8bit 7bit 8bit 9bit 8bit 9bit synchronous parity 2 stop bit 1 stop bit synchronous 0 0 0 0 0 0 0 synchronous bit converter transmit register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 stop bit parity bit t x d i ?? no parity transmit buffer register 8 bit 7 bit 7bit 9bit synchr- onous 8bit 9bit synchronous parity 2 stop bit stop bit 1 stop bit ?? data bus(odd) data bus(even) synchronous 7bit 8bit 9bit /lsb msb t x epty 76543210 r/c tcs 1 tcs 0 brg count source select bit 0 0 : select pf 2 0 1 : select pf 16 1 0 : select pf 64 1 1 : select pf 512 cts, rts select bit 0 : select cts 1 : select rts transmit register empty bit cts, rts enable bit 0 : enable cts, rts 1 : disable cts, rts (input/output port) transfer format select bit (note) 0 : lsb first 1 : msb first 76543210 re ri oer fer per sum ti te transmit enable flag transmit buffer empty flag receive enable flag receive complete flag overrun error flag framing error flag parity error flag error sum flag uart 0 transmit/receive control register 0 uart 1 transmit/receive control register 0 addresses 34 16 3c 16 uart 0 transmit/receive control register 1 uart 1 transmit/receive control register 1 addresses 35 16 3d 16 note : this bit is valid in clock synchronous mode. fix this bit to ??in uart mode.
47 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer clock synchronous serial communi- cation a case where communication is performed between two clock syn- chronous serial i/o ports as shown in figure 59 will be described. (the transmission side will be denoted by subscript j and the receiv- ing side will be denoted by subscript k.) bit 0 of the uartj transmit/receive mode register and uartk transmit/receive mode register must be set to 1 and bits 1 and 2 must be 0. the length of the transmission data is fixed at 8 bits. bit 3 of the uartj transmit/receive mode register of the clock send- ing side is cleared to 0 to select the internal clock. bit 3 of the uartk transmit/receive mode register of the clock receiving side is set to 1 to select the external clock. bits 4, 5 and 6 are ignored in clock synchronous mode. bit 7 must always be 0. the clock source is selected by bit 0 (tcs 0 ) and bit 1 (tcs 1 ) of the clock-sending-side uartj transmit/receive control register 0. as shown in figure 54, the selected clock is divided by (n+1), then by 2, is passed through a transmission control circuit, and is output as transmission clock clkj. therefore, when the selected clock is pfi, bit rate = pf i / {(n+1) 2} on the clock receiving side, the tcs 0 and tcs 1 bits of the uartk transmit/receive control register 0 are ignored because an external clock is selected. bit 2 of the clock-sending-side uartj transmit/receive control reg- ister 0 is cleared to 0 to select ctsj input. bit 2 of the clock receiv- ing side is set to 1 to select rtsk output. bit 4 of the uart transmit/receive control register 0 is used to de- termine whether to use cts or rts signal. bit 4 must be 0 when cts or rts signal is used. bit 4 must be 1 when cts and rts sig- nals are not used. when cts and rts signals are not used, cts/ rts pin can be used as a normal port. the case using cts and rts signals are explained below. however, when cts and rts signals are not used, there are no condition of ctsj input, and there is no rtsk output. fig. 59 clock synchronous serial communication uartj transmit register txdj rxdj clkj ctsj uartj transmit buffer register uartj receive buffer register uartj receive register uartj transmit/receive mode register uartj transmit/receive control register 0 uartj transmit/receive control register 1 0 00 0 t x epty tcs 1 tcs 0 re ri oer fer per sum ti te 0 uartk transmit register uartk transmit buffer register uartk receive buffer register uartk receive register uartk transmit/receive mode register uartk transmit/receive control register 0 uartk transmit/receive control register 1 0 11 0 1 t x epty msb /lsb re ri oer fer per sum ti te 0 1 txdk rxdk clkk rtsk msb /lsb
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 48 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer transmission transmission is started when bit 0 (tej flag) of uartj transmit/re- ceive control register 1 is 1, bit 1 (tij flag) of one is 0, and ctsj input is l. as shown in figure 60, data is output from t x dj pin each time when transmission clock clkj changes from h to l. the data is output from the least significant bit. the tij flag indicates whether the transmit buffer register is empty or not. it is cleared to 0 when data is written in the transmit buffer reg- ister and set to 1 when the contents of the transmit buffer register is transferred to the transmit register. when the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmission start condition is satisfied. if bit 2 of uartj transmit/receive control reg- ister 0 is 1, ctsj input is ignored, and transmission start is con- trolled only by the tej flag and tij flag. once transmission has started, the tej flag, tij flag, and ctsj signals are ignored until data transmission completes. therefore, transmission is not interrupt when ctsj input is changed to h during transmission. the transmission start condition indicated by tej flag, tij flag, and ctsj is checked while the t end j signal (shown in figure 60) is h. therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and tij flag is cleared to 0 before thet end j signal goes h. bit 3 (t x eptyj flag) of uartj transmit/receive control register 0 changes to 1 at the next cycle just after the t end j signal goes h and changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission has completed. when the tij flag changes from 0 to 1, the interrupt request bit in the uartj transmit interrupt control register is set to 1. in only uart0, data can be output to a maximum of 3 external re- ceive devices. this is realized under the condition in which the inter- nal clock is selected and the transmission clock is output from one of pins clk 0 , clks 0 (multiplexed with r x d 0 ) and clks 1 (multiplexed with cts 0 /rts 0 ). make sure that do not switch the selection of the clock during transmission. figure 61 shows an external connection example. plural output of transmit clock mode is set with bits 1 and 0 of the particular function select register 1. additionally, it is necessary to se- lect the internal clock, disable cts and rts, receive and d-a output with the uart0 transmit/receive mode register, uart0 transmit/ receive control registers 0 and 1, and a-d control register 1. figure 62 shows the relevant registers bit configuration in plural output of transmit clock mode and figure 63 shows the particular function se- lect register 1 bit configuration . table 6 shows the function of the particular function select register 1s bits 1 and 0, which is the output pin of transmit clock select bits: tc 1 and tc 0 . according to this table, select the clk 0 , clks 0 or clks 1 pin corresponding to the contents of tc 1 and tc 0 , and out- put the transmit clock. fig. 60 clock synchronous serial i/o timing transmission clock te j 1/pf i (n + 1) 2 1/pf i (n + 1) 2 ti j cts j write in transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 transmit register ? transmit buffer register stopped because te j = ?? clk j t endj t x d j t x epty j
49 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer output pin of trans- mit clock select bits table 6. output pin of transmit clock select bits and pins function tc 1 0 0 1 1 tc 0 0 1 0 1 pin name p8 1 /clk 0 clk 0 clk 0 h h p8 2 /r x d 0 r x d 0 h (note) clks 2 h (note) p8 0 /cts 0 /rts 0 /da 0 p8 0 /cts 0 /rts 0 /da 0 p8 0 p8 0 clks 1 note: it outputs h when bit 2 of the port p8 direction register is 1, and it becomes floating when bit 2 is 0. fig. 62 relevant registers except special function select register 1 bit configuration in plural output of transmit clock mode 0 0 1 : clock synchronous 0 : internal clock this bit must be ?? uart0 transmit/receive mode register 76543210 1 0 0 0 0 address 30 16 1 : disable cts, rts uart0 transmit/receive control register 0 76543210 1 address 34 16 0 : disable receive uart0 transmit/receive control register 1 76543210 0 address 35 16 0 : disable d-a output a-d control register 1 76543210 0 address 1f 16 fig. 61 external connection example in plural output of transmit clock mode uart0 d in clk note: this is available in clock synchronous serial i/o, using internal clock and transmission mode. clks 1 t x d 0 clks 0 clk 0 d in clk d in clk receive receive starts when bit 2 (rek flag) of uartk transmit/receive control register 1 is set to 1. the rtsk output is h when the rek flag is 0 and goes l when the rek flag changed to 1 and the tik flag did to 0. it goes back to h when receive starts. the tik flag is cleared to 0 by write dummy data to the transmit buffer register. it is ready to receive when rtsk output is l. the data from the rxdk pin is retrieved and the contents of the re- ceive register is shifted by 1 bit each time when the transmission clock clkj changes from l to h. when an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and bit 3 (rik flag) of uartk transmit/receive control regis- ter 1 is set to 1. in other words, the setting 1 to the rik flag indi- cates that the receive buffer register contains the received data. when the rik flag changes from 0 to 1, the interrupt request bit in the uartk receive interrupt control register is set to 1. bit 4 (oerk flag) of uartk transmit/receive control register 1 is set to 1 when the next data is transferred from the receive register to the receive buffer register while rik flag is 1, and indicates that the next data was transferred to the receive register before the contents of the re- ceive buffer register was read. rik flag is automatically cleared to 0 when the low-order byte of the receive buffer register is read or when the rek flag is cleared to 0. the oerk flag is cleared when the rek flag is cleared or port p8 is set to a parallel port. bit 5 (ferk flag), bit 6 (perk flag), and bit 7 (sumk flag) are ignored in clock synchro- nous mode. when reading the contents of the receive buffer register, the re- ceived data is pulled from the least significant bit (lsb) in the re- ceived order if bit 7 (tem) of the uartj transmit/receive control registers 0 is 0. if bit 7 (tem) is 1, the received data is pulled from the most significant bit (msb). as shown in figure 54, with clock synchronous serial communica- tion, data cannot be received unless the transmitter is operating be- cause the receive clock is created from the transmission clock. therefore, the transmitter must be operating even when there is no need to sent data from uartk to uartj.
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 50 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer register a-d control register 1 particular function select register 0 particular function select register 1 address 1f 16 6c 16 6d 16 bit 5 0, 1, 5, 6 2, 3, 4 register waveform output mode register dead-time timer pulse output data register 1 pulse output data register 0 timer a write flag int 4 interrupt control register address 1a 16 1b 16 1c 16 1d 16 45 16 6e 16 notes 1: bits 2, 3, and 4 can be re-write after bit 5 (expansion function select bit) is set to ?.? 2: after bit 5 is set to ??once, bit 5 cannot be cleared to ??except external reset and software reset. 3: bits 6 and 7 are write-only bits and undefined at read. do not use seb or clb insturuction when setting bits 0?. transmit clock output pin select bit 00 : normal mode (output only to clk 0 ) 01 : plural clocks specified; output to clk 0 10 : plural clocks specified; output to clks 0 11 : plural clocks specified; output to clks 1 internal clock stop select bit at wit (note 1) 0 : clock for peripheral function and watchdog timer are operating at wit 1 : internal clock except that for oscillation circuit and watchdog timer are stopped at wit 76543210 particular function select register 1 (6d 16 ) watchdog timer? select bit (note 1) 0 : exclusive clock deviding circuit output (wf 512 , wf 32 ) is used as clock for watchdog timer. clock (wf 512 , wf 32 ) for watchdog timer does not change in hold. 1 : clock for peripheral device deviding circuit output (pf 512 , pf 32 ) is used as clock for watchdog timer. clock (pf 512 , pf 32 ) for watchdog timer changes in hold. watchdog timer exclusive clock dividing circuit is stopped. signal output stop select bit (note 1) refer to table 8. expansion function select bit (note 2) refer to figure 62. pull-up select bit 0 (note 3) 0 : with no pull-up for p5 7 , p5 6 , p5 5 , p5 4 1 : with pull-up for p5 7 , p5 6 , p5 5 , p5 4 pull-up select bit 1 (note 3) 0 : with no pull-up for p8 0 1 : with pull-up for p8 0 tc 1 tc 0 control bits affected by expansion function select bit control registers affected by expansion function select register fig. 63 particular function select register 1 bit configuration
51 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer selection of transfer format in clock synchronous serial communication, transfer format can be selected by bit 7 of the transmit/receive control register 0. when bit 7 is 0, transfer format is lsb first. when bit 7 is 1, transfer format is msb first. this function is realized by changing connection relation between the transmit buffer register and the receive buffer register when writ- ing transmit data to the transmit buffer register or reading receive data from the receive buffer register. accordingly, the transmitters operation is the same in both transfer formats. figure 64 shows the connection relation. fig. 64 connection relation between transmit buffer register, receive buffer register, and data bus bit 7 in transmit/receive control register 0 write to transmit buffer register read from receive buffer register 0 (lsb first) 1 (msb first) transmit buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 transmit buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 receive buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 receive buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 52 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer asynchronous serial communication asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. the operation is the same for all data lengths. the following is the description for 8-bit asynchronous communica- tion. with 8-bit asynchronous communication, bit 0 of uarti transmit/ receive mode register is 1, bit 1 is 0, and bit 2 is 1. bit 3 is used to select an internal clock or an external clock. if bit 3 is 0, an internal clock is selected and if bit 3 is 1, then external clock is selected. if an internal clock is selected, bit 0 (tcs 0 ) and bit 1 (tcs 1 ) of uarti transmit/receive control register 0 are used to se- lect the clock source. when an internal clock is selected for asyn- chronous serial communication, the clki pin can be used as a normal i/o pin. the selected internal or external clock is divided by (n+1), then by 16, and is passed through a control circuit to create the uart trans- mission clock or uart receive clock. therefore, the transmission speed can be changed by changing the contents (n) of the bit rate generator. if the selected clock is an inter- nal clock pfi or an external clock f ext , bit rate = (pfi or f ext ) / {(n+1) 16} bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits. bit 5 is a select bit of odd parity or even parity. in the odd parity mode, the parity bit is adjusted so that the sum of 1s in the data and parity bit is always odd. in the even parity mode, the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always even. bit 6 is the parity bit select bit which indicates whether to add parity bit or not. bits 4 to 6 must be set or reset according to the data format used in the communicating devices. bit 7 is the sleep select bit. the sleep mode is described later. the uarti transmit/receive control register 0 bit 2 is used to deter- mine whether to use ctsi input or rtsi output. ctsi input is used if bit 2 is 0 and rtsi output is used if bit 2 is 1. if ctsi input is selected, the user can control whether to stop or start transmission by external ctsi input. bit 4 of the uart transmit/receive control register 0 is used to de- termine whether to use cts or rts signal. bit 4 must be 0 when cts or rts signal is used. bit 4 must be 1 when cts or rts sig- nal is not used. when cts or rts signal is not used, cts/rts pin can be used as a normal port. the case using cts and rts signals are explained below. however, when cts and rts signals are not used, there are no condition of ctsi input, and there is no rtsi out- put. clear uartj transmit/receive control register 0 bit 7 to 1 in asyn- chronous communication.
53 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer once transmission has started, the tei flag, tii flag, and ctsi signal (if ctsi input is selected ) are ignored until data transmission is com- pleted. therefore, transmission does not stop until it completes event if the tei flag is cleared during transmission. the transmission start condition indicated by tei flag, tii flag, and ctsi is checked while the t end i signal shown in figure 65 is h. therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and tii flag is cleared to 0 before the t end i signal goes h. bit 3 (t x eptyi flag) of uarti transmit/receive control register 0 changes to 1 at the next cycle just after the t end i signal goes h and changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission is completed. when the tii flag changes from 0 to 1, the interrupt request bit of the uarti transmit interrupt control register is set to 1. transmission transmission is started when bit 0 (tei flag) of uarti transmit/re- ceive control register 1 is 1, bit 1 (tii flag) is 0, and ctsi input is l if ctsi input is selected. as shown in figures 65 and 66, data is output from the t x di pin with the stop bit or parity bit specified by bits 4 to 6 of uarti transmit/receive mode register. the data is output from the least significant bit. the tii flag indicates whether the transmit buffer is empty or not. it is cleared to 0 when data is written in the transmit buffer, and is set to 1 when the contents of the transmit buffer register is transferred to the transmit register. when the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmit start condi- tion is satisfied. fig. 65 transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected fig. 66 transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected (1/pf i or 1/f ext ) (n + 1) 16 written in transmit buffer register transmission clock te i ti i cts i t endi t x d i t x epty i d 0 d 1 st start bit parity bit stop bit d 2 d 3 d 4 d 5 d 6 d 7 pspstd 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 psp std 0 d 1 transmit register ? transmit buffer register stopped because te i = ?? (1/pf i or 1/f ext ) (n + 1) 16 written in transmit buffer register transmission clock te i ti i t endi t x d i t x epty i d 0 d 1 st d 2 d 3 d 4 d 5 d 6 d 7 d 8 sp sp st d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 sp sp st d 0 d 2 d 1 transmit register ? transmit buffer register stopped because te i = ?? start bit stop bit stop bit
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 54 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer to 0 when reading the low-order byte of the receive buffer register or when writing 0 to the rei flag or when setting to a parallel port. the oeri and sumi flags are cleared to 0 when writing 0 to the rei flag or when setting to a parallel port. the sumi flag is cleared to 0 when the oeri, feri, peri flags are cleared to 0 all. sleep mode the sleep mode is used to communicate only between certain micro- computers when multiple microcomputers are connected through serial i/o. the microcomputer enters the sleep mode when bit 7 of uarti transmit/receive mode register is set to 1. the operation of the sleep mode for an 8-bit asynchronous commu- nication is described below. when sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asyn- chronous communication and bit 8 if 9-bit asynchronous communi- cation) of the received data is 0. also the rii, oeri, feri, peri, and the sumi flag are unchanged. therefore, the interrupt request bit of the uarti receive interrupt control register is also unchanged. normal receive operation takes place when bit 7 of the received data is 1. the following is an example of how the sleep mode can be used. the main microcomputer first sends data: bit 7 is 1 and bits 0 to 6 are set to the address of the subordinate microcomputer to be com- municated with. then all subordinate microcomputers receive this data. each subordinate microcomputer checks the received data, clears the sleep bit to 0 if bits 0 to 6 are its own address and sets the sleep bit to 1 if not. next, the main microcomputer sends data with bit 7 cleared. then the microcomputer which cleared the sleep bit will receive the data, but the microcomputers which set the sleep bit to 1 will not. in this way, the main microcomputer is able to com- municate only with the designated microcomputer. receive receive is enabled when bit 2 (rei flag) of uarti transmit/receive control register 1 is set to 1. as shown in figure 67, the frequency divider circuit (1/16) at the receiving side begin to work when a start bit arrives and the data is received. if rtsi output is selected by setting bit 2 of uarti transmit/receive control register 0 to 1, the rtsi output is h when the rei flag is 0. when the rei flag changes to 1, the rtsi output goes l to in- dicate receive ready and returns to h once receive has started. in other words, rtsi output can be used to determine externally whether the receive register is ready to receive. the entire transmission data bits are received when the start bit passes the final bit of the receive block shown in figure 56. at this point, the contents of the receive register is transferred to the receive buffer register and bit 3 (rli flag) of uarti transmit/receive control register 1 is set to 1. in other words, the rii flag indicates that the receive buffer register contains data when it is set to 1. if rtsi out- put is selected, rtsi output goes l to indicate that the register is ready to receive the next data. the interrupt request bit of the uarti receive interrupt control regis- ter is set to 1 when the rii flag changes from 0 to 1. bit 4 (oeri flag) of uarti transmit/receive control register 1 is set to 1 when the next data is transferred from the receive register to the receive buffer register while the rii flag is 1, in other words, when an overrun error occurs. if the oeri flag is 1, it indicates that the next data has been transferred to the receive buffer register before the contents of the receive buffer register has been read. bit 5 (feri flag) is set to 1 when the number of stop bits is less than required (framing error). bit 6 (peri flag) is set to 1 when a parity error occurs. bit 7 (sumi flag) is set to 1 when either the oeri flag, feri flag, or the peri flag is set to 1. therefore, the sumi flag can be used to determine whether there is an error. the setting of the rii flag, oeri flag, feri flag, and the peri flag is performed while transferring the contents of the receive register to the receive buffer register. the rli, feri, and peri flags are cleared fig. 67 receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected start bit stop bit start bit d 0 d 1 d 7 check to be ??level starting at the falling edge of start bit data fetched pf i or f ext re i r x d i receive clock ri i rts i
55 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer a-d converter the a-d converter is a 10-bit successive approximation converter. the use of a-d converter or the use of comparator can be selected for each a-d input pin. the contents of the comparator function se- lect register specify it. figure 68 shows a block diagram of the a-d converter. fig. 68 a-d converter block diagram ladder network v ref connection select bit av ss v ref control circuit 1 a-d register 0 (21 16 ) data bus (odd) data bus (even) compa- rator an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 /ad trg address address a-d register 0 (20 16 ) a-d register 1 (23 16 ) a-d register 1 (22 16 ) a-d register 2 (25 16 ) a-d register 2 (24 16 ) a-d register 3 (27 16 ) a-d register 3 (26 16 ) a-d register 4 (29 16 ) a-d register 4 (28 16 ) a-d register 5 (2b 16 ) a-d register 5 (2a 16 ) a-d register 6 (2d 16 ) a-d register 6 (2c 16 ) a-d register 7 (2f 16 ) a-d register 7 (2e 16 ) successive approximation register selector a-d conversion speed selection 1/2 f(x in ) clock source select bit (bit 6 of processor mode register 1) 1 0 1 0 pf 2 pf 8 pf 4 pf 2 clock source for peripheral devices select bit (bit 2 of processor mode register 1) 1/2 1/2 1/2 f ad f 1 f 1 selector selector comparator function select register (0: a-d converter, 1: comparator) vref comparator result register (address 66 16 ) a-d control register 1 (address 1f 16 ) a-d control register 0 (address 1e 16 ) (address 64 16 ) decoder frequency select flag 0, 1
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 56 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer figure 69 shows the comparator function select register (address 64 16 ) bit configuration. bits 7 to 0 correspond to channels 7 to 0 re- spectively. each channel can be selected as either an a-d converter or a comparator. when the bit is 0, the channel corresponding to it functions as a 10-bit or an 8-bit a-d converter. when the bit is 1, the channel functions as a comparator. when selecting an a-d converter, an input voltage to a selected ana- log input pin is a-d converted and the result is stored into the a-d register. when selecting a comparator, d-a conversion is performed to the value of which high-order 8 bits are the value stored in an even ad- dress of the a-d converter and of which low-order 2 bits are 10 2 . then, this d-a converted value is compared with the voltage sup- plied to an analog input pin. after the comparison, when the voltage supplied to an analog input pin is higher, 1 is stored into the com- parator result register (address 66 16 ) shown in figure 70. when it is lower, 0 is stored into that register. be sure to perform only read to the a-d register of which channel is selected as an a-d converter, and perform only write to the a-d reg- ister of which channel is selected as a comparator. additionally, do not write to the comparator function select register and the a-d reg- ister while an a-d converter or a comparator is operating. port direction registers bits corresponding to pins to be a-d con- verted must be 0 (input mode) because analog input ports are mul- tiplexed with port p7. figure 71 shows the bit configuration of the a-d control register 0 (address 1e 16 ) and the a-d control register 1 (address 1f 16 ). an operation clock ( f ad ) of an a-d converter or a comparator can be selected with bit 7 of the a-d control register 0 and bit 4 of the a-d control register 1. when bit 4 (frequency select flag 1) of the a-d control register 1 is 0, f ad becomes pf 8 when bit 7 (frequency select flag 0) of the a-d control register 0 is 0, f ad becomes pf 4 when bit 7 of the a-d con- trol register 0 is 1. when the frequency select flag 1 is 1, f ad becomes pf 2 when the frequency select flag 0 is 0, f ad becomes f 1 when the frequency select flag 0 is 1. the last case is used when f 1 is forcibly used as f ad in high-speed running (f(x in ) > f 1 > 12.5 mhz). however, this se- lection is available only in 8-bit resolution mode. f ad during a-d conversion must be 250 khz or more because the comparator uses a capacity coupling amplifier. bit 3 of a-d control register 1 is used to select whether to regard the conversion result as 10-bit or as 8-bit data. the conversion result is regarded as 10-bit data when bit 3 is 1 and as 8-bit data when bit 3 is 0. when the conversion result is used as 10-bit data, the low-order 8 bits of the conversion result is stored in the even address of the cor- responding a-d register and the high-order 2 bits are stored in bits 0 and 1 at the odd address of the corresponding a-d register. bits 2 to 7 of the a-d register odd address are 000000 2 when read. when the conversion result is used as 8-bit data, the high-order 8 bits of the 10-bit a-d conversion result are stored in even address of the corresponding a-d register. in this case, the value at the a-d registers odd address is 00 16 when read. whether to connect the reference voltage input (v ref ) with the lad- fig. 69 comparator function select register bit configuration fig. 70 comparator result register bit configuration der network or not depends on bit 5 of the a-d control register 1. the v ref pin is connected when bit 5 is 0 and is disconnected when bit 5 is 1 (high impedance state). when a-d or d-a conversion is not performed, current from the v ref pin to the ladder network can be cut off by disconnecting ladder net- work from the v ref pin. before starting a-d or d-a conversion, wait for 1 m s or more after clearing bit 5 to 0. note: do not access with the seb or clb instruction. 76543210 comparator function select register ??: select a-d converter ??: select comparator an 0 pin comparator function select bit an 1 pin comparator function select bit an 2 pin comparator function select bit an 3 pin comparator function select bit an 4 pin comparator function select bit an 5 pin comparator function select bit an 6 pin comparator function select bit an 7 pin comparator function select bit address 64 16 76543210 comparator result register ??: ani input level is lower than set digital value ??: ani input level is higher than set digital value an 0 pin comparator result bit an 1 pin comparator result bit an 2 pin comparator result bit an 3 pin comparator result bit an 4 pin comparator result bit an 5 pin comparator result bit an 6 pin comparator result bit an 7 pin comparator result bit address 66 16
57 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer operation mode the operation mode is selected by bits 3 and 4 of a-d control regis- ter 0 and bit 2 of a-d control register 1. the available operation modes are one-shot, repeat, single sweep, repeat sweep 0, and re- peat sweep 1. either an a-d converter or a comparator can be se- lected respectively for every pin in the following 5 modes. the following description applies to the case where the bit of the com- parator function select register is 0 and an a-d converter is se- lected. it also applies to a comparators operation except that an a-d conversion is changed to a comparator operation and the result of a comparison is stored into the comparator result register. (1) one-shot mode one-shot mode is selected when bits 3 and 4 of a-d control register 0 are 0 and bit 2 of a-d control register 1 is 0. the a-d conversion pins are selected with bits 0 to 2 of a-d control register 0. a-d con- version can be started by a software trigger or by an external trigger. a software trigger is selected when bit 5 of a-d control register 0 is 0 and an external trigger is selected when it is 1. when a software trigger is selected, a-d conversion or comparator operation is started when bit 6 (a-d conversion start flag) is set to 1. when the bit of comparator function select register is 0 and bit 3 of a-d control register 1 is 1, a-d conversion ends after 59 f ad cycles, and the interrupt request bit of the a-d interrupt control regis- ter is set to 1. at the same time, a-d control register 0 bit 6 (a-d conversion start bit) is cleared to 0 and a-d conversion stops. the result of a-d conversion is stored in the a-d register corresponding to the selected pin. when the bit of the comparator function select register is 1, a com- parator operation ends after 14 f ad cycles and the interrupt request bit of the a-d interrupt control register is set to 1. at the same time, the a-d control register 0 bit 6 (a-d conversion start bit) is cleared to 0 and the comparator operation stops. the result of the comparison is stored into the bit of the comparator result register cor- responding to the selected pin. if an external trigger is selected, a-d conversion starts when the a-d conversion start bit is 1 and the ad trg input changes from h to l. in this case, the pins that can be used for a-d conversion are an 0 to an 6 because the ad trg pin is multiplexed with analog voltage in- put pin an 7 . this operation is the same as that for software trigger except that the a-d conversion start bit is not cleared after a-d con- version and a retrigger can be available during a-d conversion. fig. 71 a-d control register bit configuration bit 1 0 0 1 1 0 0 1 1 bit 0 0 1 0 1 0 1 0 1 a-d conversion frequency select bit f(x in )/16 f(x in )/8 f(x in )/4 f(x in )/2 (note 3) f(x in )/8 f(x in )/4 f(x in )/2 f ad bit 6 at address 5f 16 (note 1) bit 2 at address 5f 16 (note 2) 0 0 1 notes1, 2: refer to figure 9 processor mode register 1 bit configuration. 3: when f(x in ) > 25 mhz, this can be selected only in 8-bit resolution mode. bit 1 0 0 1 1 0 0 1 1 bit 0 0 1 0 1 0 1 0 1 a-d conversion frequency select bit f(x in )/8 f(x in )/4 f(x in )/2 f(x in ) (note 4) f(x in )/4 f(x in )/2 f(x in ) f ad bit 6 at address 5f 16 (note 1) bit 2 at address 5f 16 (note 2) 1 0 1 notes 4: when f(x in ) > 12.5 mhz, this can be selected only in 8-bit resolution mode. 5: when the expansion function select bit (bit 5 of particular function select register 1 ; refer to fig. 63) is 1, bit 5 can be written and changed. a-d control register 0 address 1e 16 76543210 analog input select bit 0 0 0 : select an 0 0 0 1 : select an 1 0 1 0 : select an 2 0 1 1 : select an 3 1 0 0 : select an 4 1 0 1 : select an 5 1 1 0 : select an 6 1 1 1 : select an 7 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 trigger select bit 0 : software trigger 1 : ad trg input trigger a-d conversion start bit 0 : stop a-d conversion 1 : start a-d conversion a-d conversion frequency select bit 0 76543210 a-d sweep pin select bit when single sweep or repeat sweep mode 0 is selected 0 0 : an 0 , an 1 0 1 : an 0 Can 3 1 0 : an 0 Can 5 1 1 : an 0 Can 7 when repeat sweep mode 1 is selected 0 0 : an 0 0 1 : an 0 , an 1 1 0 : an 0 Can 2 1 1 : an 0 Can 3 a-d operation mode select bit 1 0 : other than repeat sweep mode 1 1 : repeat sweep mode 1 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode a-d converter frequency select bit 1 v ref connection select bit (note 5) 0 : v ref is connected 1 : v ref is not connected these bits are not used for a-d converter. (2 pins) (4 pins) (6 pins) (8 pins) (1 pins) (2 pins) (3 pins) (4 pins) a-d control register 1 address 1f 16
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 58 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (2) repeat mode repeat mode is selected when bit 3 of a-d control register 0 is 1, bit 4 is 0 and bit 2 of a-d control register 1 is 0. the operation of this mode is the same as the operation of one-shot mode except that when a-d conversion of the selected pin is com- plete and the result is stored in the a-d register, conversion does not stop, but is repeated. no interrupt request is generated in this mode. furthermore, if soft- ware trigger is selected, the a-d conversion start bit is not cleared. the contents of the a-d register can be read at any time. be sure not to write to the a-d register corresponding to the pins se- lected for a comparator during operation. (3) single sweep mode single sweep mode is selected when bit 3 of a-d control register 0 is 0, bit 4 is 1 and bit 2 of a-d control register 1 is 0. in the single sweep mode, the number of analog input pins to be swept can be selected. analog input pins are selected by bits 1 and 0 of the a-d control register 1 (address 1f 16 ). two pins, four pins, six pins, or eight pins can be selected as analog input pins, depending on the contents of these bits. a-d conversion is performed only for selected input pins. after a-d conversion is performed for input of an 0 pin, the conversion result is stored in a-d register 0, and in the same way, a-d conversion is per- formed for selected pins one after another. after a-d conversion is performed for all selected pins, the sweep is stopped. a-d conversion can be started with a software trigger or with an ex- ternal trigger input. a software trigger is selected when bit 5 is 0 and an external trigger is selected when it is 1. when a software trigger is selected, a-d conversion is started when a-d control register 0 bit 6 (a-d conversion start bit) is set to 1. when a-d conversion of all selected pins end, the interrupt request bit of the a-d conversion interrupt control register is set to 1. at the same time, a-d conversion start bit is cleared to 0 and a-d conver- sion stops. when an external trigger is selected, a-d conversion starts when the a-d conversion start bit is 1 and the ad trg input changes from h to l. in this case, the a-d conversion result which is stored in the a- d register 7 becomes invalid because the ad trg pin is multiplexed with an 7 pin. the operation by external trigger is the same as that by software trig- ger except that the a-d conversion start bit is not cleared to 0 after a-d conversion and a retrigger can be available during a-d conver- sion. (4) repeat sweep mode 0 repeat sweep mode 0 is selected when bit 3 of a-d control register 0 is 1, bit 4 is 1 and bit 2 of a-d control register 1 is 0. the difference from the single sweep mode is that a-d conversion does not stop after conversion for all selected pins, but repeats again from the an 0 pin. the repeat is performed among the selected pins. also, no interrupt request is generated. furthermore, if software trig- ger is selected, the a-d convension start bit is not cleared. the a-d register can be read at any time. be sure not to write to the a-d register corresponding to the pins se- lected for a comparator during operation. (5) repeat sweep mode 1 repeat sweep mode 1 is selected when bit 3 of a-d control register 0 is 1, bit 4 is 1 and bit 2 of a-d control register 1 is 1. the difference from the repeat sweep mode 0 is that a-d conversion for one unselected pin is performed each time when a-d conversion for selected pins is completed and a-d conversion is repeated once again from an 0 pin. the number of analog input pins to be swept is also different. the analog input pins for repeatedly sweep are selected with bits 1 and 0 of a-d control register 1. the contents of these pins are used to select one pin, two pins, three pins, or four pins. the unselected pins are converted from the pin next to the pins se- lected as repeat sweep pins. no interrupt request is generated. fur- thermore, if software trigger is selected, the a-d conversion start bit is not cleared. the a-d register can be read at any time. be sure not to write to the a-d register corresponding to the pins se- lected for a comparator during operation. note: clear the interrupt request bit of the a-d interrupt control reg- ister (bit 3 at address 70 16 ) before using the a-d interrupt. it is because the interrupt request bit is undefined just after reset.
59 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 72 d-a converter block diagram d-a converter the d-a converter is an 8-bit r-2r method d-a converter and con- sists of two independent d-a converters. figure 72 shows the block diagram of the d-a converter and figure 73 shows the bit configura- tion of a-d control register 1. d-a conversion is performed by writing a value in the corresponding d-a register. the conversion result is output by bits 6 and 7 of a-d control register 1 (address 1f 16 ). when bit 7 is 1, the conversion result is output from da 0 pin. when bit 6 is 1, the conversion result is output from da 1 pin. the output analog voltage v is determined according to the value n (n is a decimal number) set in the d-a register. v = v ref n/256 (n = 0 to 255) v ref : reference voltage the d-a output enable bit is cleared to 0 at reset. whether to con- nect the reference voltage input (v ref ) with the ladder network or not depends on bit 5 of the a-d control register 1. the v ref pin is con- nected when bit 5 is 0 and is disconnected when bit 5 is 1 (high impedance state). fig. 73 a-d control register 1 bit configuration 7 6543210 not used for d-a converter v ref connection select bit (note) 0 : v ref is connected 1 : v ref is not connected d-a 1 output enable bit 0 : disable output 1 : enable output d-a 0 output enable bit 0 : disable output 1 : enable output a-d control register 1 address 1f 16 when a-d or d-a conversion is not performed, current from the v ref pin to the ladder network can be cut off by disconnecting ladder net- work from the v ref pin. before starting a-d or d-a conversion, wait for 1 m s or more after clearing bit 5 to 0. an external buffer must be connected when con- necting to a low impedance load because there is no built-in d-a out- put buffer. note : when the expansion function select bit (bit 5 of peripheral function select register 1 ; refer to fig. 63) is 1, bit 5 can be written and changed. r-2r ladder network d-a 0 output enable bit d-a register 0 (address 68 16 ) d-a 0 pin av ss r-2r ladder network data bus (even) d-a 1 output enable bit d-a register 1 (address 6a 16 ) d-a 1 pin av ss v ref v ref connection select
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 60 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer watchdog timer the watchdog timer is used to detect unexpected execution se- quence caused by software runaway and others. figure 74 shows the block diagram of the watchdog timer. the watchdog timer consists of a 12-bit binary counter. the watchdog timer counts clock wf 32 /pf 32 , which is obtained by di- viding the peripheral devices clock pf 2 by 16; or clock wf 512 /pf 512 , which is obtained by doing it by 256. the watchdog timer frequency select register shown in figure 75 selects which clock is counted. wf 512 /pf 512 is selected when its contents are 0, and wf 32/ pf 32 is selected when they are 1. they are cleared to 0 after reset. the watchdog timer clock select bit (bit 3 of particular function select register 1; figure 62) selects use of clock wf 512 /wf 32 or pf 512 /pf 32 as the clock source of watchdog timer. when selecting wf 512 /wf 32 , the clock source of watchdog timer (wf 512 /wf 32 ) is not active during hold state. when selecting pf 512 /pf 32 , the clock source of watchdog timer (pf 512 /pf 32 ) is active during hold state, however, current con- sumption can be reduced. it is because the wf 512 /wf 32 division cir- cuit stops. fff 16 is set in the watchdog timer when l or 2vcc is applied to the reset pin, stp instruction is executed, data is written to the watch- dog timer, or the most significant bit of the watchdog timer becomes 0. after fff 16 is set in the watchdog timer, when the watchdog timer counts the clock source by 2048 counts, the most significant bit of watchdog timer becomes 0, the watchdog timer interrupt request bit is set to 1, and fff 16 is set again in the watchdog timer. normally, a program is written so that data is written in the watchdog timer before the most significant bit of the watchdog timer becomes 0. if this routine is not executed owing to unexpected program ex- ecution and others, the most significant bit of the watchdog timer becomes 0 and an interrupt is generated. the microcomputer can be reset by writing 1 to bit 3 (software re- set bit) of processor mode register 0 in the interrupt routine, de- scribed in figure 16 in the interrupt section, and generating a reset pulse. the watchdog timer stops its function when the reset pin voltage is raised to double the vcc voltage. the watchdog timer can also be used to return from when the clock is stopped by the stp instruction. refer to the section on the clock generating circuit for more details. the watchdog timer also becomes hold state during hold state and the clock input to it is stopped. watchdog timer frequency select register watchdog timer clock select bit write to watchdog timer stp instruction s r q 2vcc detection wachdog timer set fff 16 reset 1/16 1/16 wf 32 wf 512 clock source for peripheral devices pf 1/8 1/2 1/2 1/8 pf 32 pf 512 pf 16 hold request hold request address 60 16 pf 16 stp return select bit fig. 74 watchdog timer block diagram 76543210 watchdog timer frequency select register 0 : w f 512 or pf 512 selected 1 : w f 32 or pf 32 selected this bit must be fixed to 0. 6543210 0 address 61 16 fig. 75 watchdog timer frequency select register bit configuration 2
61 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer reset circuit reset is released when the reset pin is returned to h level after holding it at l level while the supply voltage is at 5v 10%. as the result, program execution starts at the address formed by setting the address a 23 Ca 16 to 00 16 , a 15 Ca 8 to the contents of address ffff 16 , and a 7 Ca 0 to the contents of address fffe 16 . figure 76 shows the status of the internal registers during reset. figure 77 shows an example of a reset circuit. when a stabilized clock is input from the external to the oscillation circuit, the reset in- put voltage must be held 0.9v or lower when the supply voltage reaches 4.5v. when connecting a resonator to the oscillation circuit, return the reset input voltage from l to h after the main-clock os- cillation is fully stabilized reset v cc v cc reset power on 4.5v 0 v 0 v 0.9v fig. 77 reset circuit example (perform careful evaluation at system design before using) input/output pins ports p0 to p8 all have the direction register and each bit can be pro- grammed for input or output. a pin becomes an output pin when the corresponding bit of direction register is 1, and an input pin when it is 0. when a pin is programmed for output, the data is written to its port latch and it is output to the output pin. when a pin is programmed for output, the contents of the port latch is read instead of the value of the pin. accordingly, a previously output value can be read correctly even when the output h voltage is lowered or the output l voltage is raised owing to an external load and others. a pin programmed as an input pin is floating, and the value input to the pin can be read. when a pin is programmed as an input pin, the data is written only in the port latch and the pin remains floating. additionally, ports p5 4 to p5 7 , p8 0 include pull-up transistors. the pull-up function of ports is selected with bits 7 and 6 of the particular function select register 1. refer to the section on interrupts for the pull-up function. figures 78 and 79 show block diagrams of ports p0 to p8 0 in the single-chip mode and e output. ports p0 to p4 are also used as pins of address, data and control signals. refer to the section on processor mode for more details.
mitsubishi microcomputers M37753M8C-XXXFP , m37753m8c-xxxhp m37753s4cfp , m37753s4chp 62 preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 76 microcomputer internal registers status after reset ( 04 16 ) address port p0 direction register 0 0000 00 16 ( 05 16 ) port p1 direction register ( 08 16 ) port p2 direction register 0000 ( 09 16 ) port p3 direction register 00 16 ( 0c 16 ) port p4 direction register 00 16 ( 0d 16 ) port p5 direction register 00 16 ( 10 16 ) port p6 direction register 00 16 ( 11 16 ) port p7 direction register 00 16 ( 14 16 ) port p8 direction register 00 16 ( 56 16 ) timer a0 mode register 00 16 ( 57 16 ) timer a1 mode register 00 16 ( 58 16 ) timer a2 mode register 00 16 ( 59 16 ) timer a3 mode register 00 16 ( 5a 16 ) timer a4 mode register 00 16 0 00 0 000 ( 1d 16 ) pulse output data register 0 0 000 0 ??? ( 1e 16 ) a-d control register 0 0 000 0 011 ( 1f 16 ) a-d control register 1 1 0 0 000 ( 34 16 ) uart 0 transmit/receive control register 0 1 0 0 000 ( 3c 16 ) uart 1 transmit/receive control register 0 0 000 0 010 ( 35 16 ) uart 0 transmit/receive control register 1 0 000 0 010 ( 3d 16 ) uart 1 transmit/receive control register 1 0 0 000 ( 42 16 ) one-shot start register 000 ( 45 16 ) timer a write register ( 1a 16 ) waveform output mode register 00 16 ( 1c 16 ) pulse output data register 1 00 16 ( 30 16 ) uart 0 transmit/receive mode register 00 16 ( 38 16 ) uart 1 transmit/receive mode register 00 16 0 000 0 000 ( 44 16 ) up-down register ( 40 16 ) count start register 00 16 0 01 0 000 ( 5b 16 ) timer b0 mode register 0 01 0 000 ( 5c 16 ) timer b0 mode register 0 01 0 000 ( 5d 16 ) timer b0 mode register 0 000 0 000 ( 5e 16 ) processor mode register 0 ( 5f 16 ) processor mode register 1 00 16 ( 60 16 ) address watchdog timer 00 0 0 0000 00 0 0 0000 00 0 0 0000 00 0 0 0000 00 0 0 0000 00 0 0 0000 00 0 0 0000 00 fff 16 ( 61 16 ) watchdog timer frequency select register ( 6d 16 ) particular function select register 1 ( 64 16 ) comparator function select register ( 66 16 ) comparator result register ( 68 16 ) d-a register 0 ( 6a 16 ) d-a register 1 ( 6c 16 ) particular function select register 0 int 2 interrupt control register processor status register ps 00 16 00 16 program bank register pg contents of ffff 16 program counter pc h contents of fffe 16 program counter pc l 0000 16 ( 6e 16 ) int 4 interrupt control register ( 6f 16 ) int 3 interrupt control register 0 00 000 ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ( 72 16 ) uart 0 receive interrupt control register ( 73 16 ) uart 1 transmit interrupt control register ( 74 16 ) uart 1 receive interrupt control register ( 77 16 ) timer a2 interrupt control register ( 78 16 ) timer a3 interrupt control register ( 79 16 ) timer a4 interrupt control register ( 7a 16 ) timer b0 interrupt control register 0 0 0 000 ( 7c 16 ) timer b2 interrupt control register 000 ( 7e 16 ) int 1 interrupt control register ( 70 16 ) a-d interrupt control register ( 71 16 ) uart 0 transmit interrupt control register ( 75 16 ) timer a0 interrupt control register ( 76 16 ) timer a1 interrupt control register 0 0 0 000 ( 7d 16 ) int 0 interrupt control register ( 7b 16 ) timer b1 interrupt control register direct page register dpr ( 7f 16 ) 0 00 1?? 0 00 ?? 0 00 data bank register dt contents of other registers and ram are not initiallzed and must be in- itiallzed by software. 000
63 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 78 block diagram for ports p0 to p8 in single-chip mode and e output (1) ? port p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 3 , p2 7 , p3 0 to p3 3 , p4 3 to p4 6 (inside dotted-line not included) port p4 0 , p4 1 , p4 7 , p5 1 , p5 3 , p6 1 to p6 7 , p8 6 (inside dotted-line included) data bus direction register port latch ? port p7 0 to p7 6 (inside dotted-line not included) ? port p7 7 (inside dotted-line included) ? port p4 2 , p8 3 , p8 7 (inside dotted-line not included) port p5 0 , p5 2 , p6 0 , p8 2 (inside dotted-line included) data bus direction register port latch ?? output ? port p5 4 , p5 6 data bus direction register port latch ?? output pull-up select data bus analog input direction register port latch
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 64 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 79 block diagram for ports p0 to p8 in single-chip mode and e output (2) ? port p5 5 , p5 7 ? port p8 0 (inside dotted-line included) ? port p8 4 (inside dotted-line not included) data bus direction register pull-up select port latch ?e data bus direction register port latch output ?? ?? ? port p8 1 , p8 5 data bus direction register port latch output cts i analog output enable d-a output ?? ?? pull-up select
65 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer clock generating circuit the clock generating circuit makes basic clocks, which activate the central processing unit (cpu), bus interface unit (biu) and internal peripheral devices, of an oscillation circuit output. figure 82 shows the block diagram of the clock generating circuit. the clock source f 1 to activate internal peripheral devices, the clock source f biu to activate the bus interface unit and the clock source f cpu to activate the cpu are made of an clock input to the x in pin. when bit 6 (clock source select bit) of processor mode register 1 is 0, the clock which is obtained by dividing an input clock to the x in pin by 2 becomes the clock source f 1 . when bit 6 is 1, the clock which is an input clock to the x in pin becomes the clock source f 1 as it is. when bit 2 (clock source for peripheral devices select bit) is 0, the clock source f 1 which is more divided by 2 becomes the standard clock for peripheral devices. when bit 2 is 1, the clock source f 1 becomes the standard clock for peripheral devices as it is. the standard clock is more divided with the division circuit shown in figure 82 and the clocks having all kinds of frequencies are made. each internal peripheral device can select one of 4 clocks, pf 2 , pf 16 , pf 64 and pf 512 , and use it. pf 2 means f(x in ), which is an oscillation circuits frequency, divided by 2 when the clock source for peripheral devices select bit is 1. it means f(x in ) divided by 4 when that bit is 0. in the case of f 1 > 12.5 mhz, fix the bit to 0. figure 80 shows a circuit example using a ceramic (or quartz crys- tal) resonator. use the manufactures recommended values for con- stants such as capacitance which differs for each resonator. figure 81 shows a circuit example inputting clocks externally. when inputting clocks externally, setting bit 1 (clock external input select bit) of particular function select register 0 (in figure 83) to 1 makes operation of the clock oscillation circuit stop, that is, the x out output stays at h, and the current consumption reduce. x in r f x out r d c in c out x in external clock source vcc vss x out open fig. 80 circuit example using a ceramic (or quartz crystal) resonator fig. 81 circuit example inputting clocks externally
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 66 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 82 clock generating circuit block diagram 0 1/2 s r q s r q 1 s pf i , wf i : represents f(x in ) divided by i when the clock source for peripheral devices is f 1 . represents f(x in ) divided by (i 5 2) when the clock source for peripheral devices is f 1 divided by 2. r q 0 1 0 hold request 1 1 0 1 0 1 0 wf 512 wf 32 pf 32 clock external input select bit x in x out internal clock stop select bit at wit interrupt request stp instruction reset wit instruction 1/2 1/8 1/2 1/2 1/8 pf 512 pf 64 pf 16 pf 2 clock source for peripheral devices select bit stp return select bit 1/8 1/2 1/16 f biu f cpu clock source for cpu operation halt request to cpu from bus interface unit caused by hold request and others wachdog timer watchdog timer frequency select register clock source select bit f 1 hold request watchdog timer clock select bit watchdog timer clock select bit wachdog timer overflow signal ready request clock source for bus interface unit operation
67 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer particular function select register 0 external clock input select bit (notes 1, 2) 0 : actuated oscillation circuit; connecting resonator 1 : stopped oscillation circuit; inputting externally generated clock standby state select bit 0 (note 1) ; when wit or stp instruction is executed in memory expansion or microprocessor mode 0 : external bus for p0 to p3 1 : port input/output for p0 to p3 standby state select bit 1 (notes 1, 3) ; in execution of wit or stp instruction 0 : h or l output for pin e 1 : h output for pin e memory allocation select bit (note 2) 0 : rom 60 kbytes, ram 2048 bytes ( rom : 001000 16 to 00ffff 16 , ram : 000080 16 to 00087f 16 ) 1 : rom 56 kbytes, ram 2048 bytes ( rom:002000 16 to 00ffff 16 , ram:000080 16 to 00087f 16 ) this bit must be fixed to 0. stp return select bit 0 : watchdog timer is used when returning from stop mode. 1 : watchdog timer is not used when returning from stop mode; the microcomputer returns at once. address 6c 16 notes 1 : after the expansion function select bit (bit 5 of particular function select register 1; figure 63) is 1, bits 1, 5 and 6 can be written and changed. 2 : to set bits 1 and 2, continuous-twice-write operation must be performed to address 6c 16 . 3 : when the signal output disable select bit = 1 and bit 6 = 1, the e pin outputs l. fig. 83 particular function select register 0 bit configulation 0 0 1 2 3 4 5 6 7
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 68 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer standby function the wit and the stp instructions make the microcomputer standby state. table 7 shows the relation between standby state and each blocks operation. the wit/stp state is terminated by interrupt acceptance or reset. accordingly, it is necessary to prepare the state in which any inter- rupt can be accepted before the wit/stp instruction is executed. wit instruction when the wit instruction is executed with the internal clock stop select bit at wit (bit 2 of particular function select register 1; figure 63) = 0, the clock sources f biu and f cpu are stopped at l, how- ever, the oscillation circuit, the clock source f 1 , and the divided clocks pf 2 to pf 512 , wf 32 , wf 512 are not stopped. accordingly, al- though the cpu and bus interface unit stop operation, internal pe- ripheral devices which use these divided clocks can operate even at wit state. otherwise, when the wit instruction is executed with the internal clock stop select bit at wit = 1, the oscillation circuit is not stopped, however, the clock source f 1 , divided clocks, and the clock sources f biu and f cpu are stopped. accordingly, in this case, all of the inter- nal peripheral devices and the watchdog timer which use divided clocks pf 2 to pf 512 , wf 32 , and wf 512 are stopped. when internal peripheral devices are not used in wit state, the lat- ter state (internal clock stop select bit at wit = 1) is more effective to reduce current consumption. make sure to set the internal clock stop select bit at wit to 1 imme- diately before the wit instruction execution and clear the bit to 0 immediately after the wit state is terminated. the wit state is terminated when an interrupt request is accepted, and the internal clock f operation is restarted. interrupt processing can immediately be executed because oscillation circuits operation is not stopped during wit state. stp instruction when the stp instruction is executed, the oscillation circuit is stopped and the clock sources f 1 , f biu and f cpu are at l. fur- thermore, fff 16 is automatically set into the watchdog timer, and its clock source is forced to connect with wf 32 when the watchdog timer clock select bit = 0, or pf 32 when the bit = 1. this connection is cut off when the most significant bit of the watchdog timer be- comes 0 or the microcomputer is reset, and the clock source is con- nected with the input depending on the contents of the watchdog timer frequency select register and the watchdog timer clock select bit. in stp state, all of the internal peripheral devices and the watch- dog timer which use divided clocks pf 2 to pf 512 , wf 32 , and wf 512 are stopped. the stp state is terminated by reset or interrupt request accep- tance, and then oscillation is restarted. at the same time, supply of the clock source f 1 and divided clocks pf 2 to pf 512 , wf 32 and wf 512 is restarted. in that condition, when the stp return select bit (bit 7 of particular function select register 0) is 0, the clock sources f biu and f cpu stop at l until the most significant bit of the watchdog timer decremented with divided clock pf 32 or wf 32 becomes 0. however, supply of the clock sources f biu and f cpu is restarted immediately after the oscillation restarts by reset. accordingly, in this case, wait for enough time to stabilize the oscillation before the reset input of h. otherwise in that condition, when the stp return select bit is 1, supply of the clock sources f biu and f cpu is restarted at the timing of the divided clock pf 16 s h to l after the oscillation restarts. this function makes it possible to immediately return from stp state when the clock supply input to the x in from the external is stabilized. even though clocks are input from the external, make sure to clear the stp return select bit to 0 if the external clock is unstable for a short time when returning from stp state instruction internal clock stop bit at wit oscillation circuit f 1 operating stopped (l) stopped (l) pf 2 to pf 512 operating stopped (h) stopped (h) f biu , f cpu stopped (l) stopped (l) stopped (l) internal peripheral devices using pf 2 to pf 512 , wf 32 , wf 512 operation enabled (watchdog timer operating) operation disabled (watchdog timer stopped) operation disabled (watchdog timer stopped) wf 2 , wf 512 operating (note 2) stopped (h) stopped (h) operation at wit/stp state wit stp 0 1 table 7 relation between standby state and each blocks operation. notes 1 : when the clock external input select bit is 1, the clock oscillation circuit stops. an external clock can be input. 2 : when the watchdog timer clock select bit is 1, wf 32 and wf 512 stop. the watchdog timer operates with pf 32 or pf 512 . operating (note 1) operating (note 1) stopped
69 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer bus cycle in wit/stp when the wit/stp instruction is executed with the standby state se- lect bit 1 (bit 6 of particular function select register 0) = 0, the clock sources f biu and f cpu or oscillation stop without waiting for completion of the bus cycle being executed. accordingly, the micro- computer may enter wit/stp state during bus access in which out- put of pin e is l. otherwise, when the wit/stp instruction is executed with the standby state select bit 1 = 1, the clock sources f biu and f cpu or oscillation stop after completion of read or write in the bus access cycle being executed. consequently, in wit/stp state, the bus be- comes the nonaccess state in which output of pin e is h. bus state in wit/stp normally, pins for the address output, data input/output and bus control signal output in the memory expansion/microprocessor mode (ports p0 to p3 in single-chip mode; refer to section on processor mode) retain the state as external bus pins when the clock sources f biu and f cpu stop in wit/stp state. however, when the wit/stp instruction is executed with the standby state select bit 0 (bit 5 of particular function select register 0) = 1, those pins function depending on the contents of each port direction register and port latch in wit/stp state like ports in single-chip mode. that is, when setting arbitrary data to the port latch and the contents of direction register to 1, that data is output from the pin; when clearing the contents of direction register to 0, the pin be- comes floating. this function makes the external bus arbitrary state in wit/stp state. when making pins floating, take consideration with an external circuit to prevent their electric potential from becoming half level of the electric potential. when writing to registers relevant to ports p0 to p3 in the memory expansion/microprocessor mode, set the standby state select bit 0 to 1 before that write. if that bit is 0, write is impossible, because addresses corresponding to registers relevant to ports p0 to p3, which are addresses 2 16 to 9 16 are the external memory areas shown in figure 86. the e pin state can arbitrarily be selected in wit/stp state in the memory expansion/microprocessor mode, too. refer to the table 8 for details. note that the function of arbitrary data output cannot be emulated using a debugger. table 8 signal output disable select bit function (bit 4 of particular function select register 1; figure 63) processor mode pin function signal output disable select bit = 0 outputs enable signal e. outputs e when accessing internal/external memory area. outputs h or l after executing wit/stp instruction outputs h when standby state select bit 1 is 1. signal output disable select bit = 1 outputs l. outputs e when accessing external memory area only. outputs h or l after executing wit/stp instruction. outputs l when standby state select bit 1 is 1 and standby state select bit 0 is 1. outputs h when standby state select bit 1 is 1 and standby state select bit 0 is 0. outputs contents of port p4 2 latch; necessary to set its direction register bit to 1. note : all functions of signal output disable select bit cannot be debugged using an debugger. memory expansion mode microprocessor mode microprocessor mode outputs clock f 1 regardless of f 1 output select bit. e e e f 1 single-chip mode
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 70 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer processor mode bits 0 and 1 of processor mode register 0 (address 5e 16 ) shown in figure 84 are used to select any mode of the single-chip mode, the memory expansion mode and the microprocessor mode. ports p0 to p3 and a part of port p4 are used as i/o pins of address, data, and control signals in the modes except the single-chip mode. figure 85 shows the functions of ports p0 to p4 in each mode. the external memory area depends on the mode. figure 86 shows the memory map for each mode. refer to figure 1 for the addresses of ram and rom in the single-chip mode. the external memory area can be accessed in the modes except the single-chip mode. the access to the external memory is affected by the byte pin. ? byte pin when accessing the external memory, the level of the byte pin is used to determine whether to use the data bus as 8-bit width or 16- bit width. the data bus has a width of 16 bits when the level of the byte pin is l, and ports p1 and p2 become the data i/o pins. the data bus has a width of 8 bits when level of the byte pin is h, and port p2 becomes data i/o pins. when accessing the internal memory, the data bus always has a width of 16 bits regardless of the byte pin level. 0 76543210 processor mode register 0 5e 16 processor mode bits 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : do not select. internal memory access bus cycle select bit (note) ; internal memory access condition in high-speed running 0 : 2- f access for internal ram; 3- f access for internal rom and sfr 1 : 2- f access for internal ram, internal rom and sfr software reset bit reset occurs when writing ??to this bit interrupt priority detection time select bit 0 0 : select case 0 shown in figure 13 0 1 : select case 1 shown in figure 13 1 0 : select case 2 shown in figure 13 test mode bit this bit must be fixed to ?.? clock f 1 output select bit 0 : no f 1 output 1 : f 1 output address note : clear bit 2 to ??in low-speed running. fig. 84 processor mode register 0 bit configuration
71 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer fig. 85 processor modes and ports p0 to p4 note : the signal output disable select bit (bit 4 of the particular function select register 1) can stop the e signal output in the single-chip mode and the f 1 output in the microprocessor mode. in the memory expansion mode or the microprocessor mode, signal e can also be fixed to h when the internal memory area is accessed. pm 1 pm 0 mode port port 0 byte = l byte = h byte = l 0 0 single-chip mode * in this case, bit 7 of processor mode regis- ter 0 is 0. 0 1 memory expansion mode * in this case, bit 7 of processor mode regis- ter 0 is 0. 1 0 microprocessor mode same as left same as left same as left same as left same as left same as left clock f 1 is output from p4 2 regardless of bit 7 of processor mode register 0 ; the others are the same as left (note) . byte = h port p3 port p4 * in this case, bit 7 of processor mode regis- ter 0 is 1. * in this case, bit 7 of processor mode regis- ter 0 is 1. i/o port e p0 0 to p0 7 e i/o port p1 0 p1 7 to e p2 0 p2 7 i/o port to e p3 0 p3 3 i/o port to e p4 0 p4 7 i/o port to f 1 p4 2 e p0 0 p0 7 (note) address a 0 to a 7 to e a 8 to a 15 p1 0 p1 7 address data(odd) to e p1 0 p1 7 address a 8 to a 15 to e a 16 to a 23 p2 0 p2 7 address data(even) to e a 16 to a 23 p2 0 p2 7 address data (even,odd) to e hlda bhe r/w ale p3 3 p3 2 p3 1 p3 0 i/o port p4 2 p4 7 e hold rdy p4 1 p4 0 to f 1 p4 2 same as above except p4 2 same as above except p4 2 port p1 port p2
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 72 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer input while e is l. when the byte pin level h, port p1 functions as an address output pin. port p2 has two functions depending on the level of the byte pin. in both cases, the i/o port function is lost. when the byte pin level is l, port p2 functions as an address out- put pin while e is h and as an even-address-data i/o pin while e is l. however, if an internal memory is read, external data is not input while e is l. when the byte pin level is h, port p2 functions as an address out- put pin while e is h and as an even- and odd-address-data i/o pin while e is l. however, if an internal memory is read, external data is not input while e is l. ports p3 0 , p3 1 , p3 2 , and p3 3 become r/w, bhe, ale, and hlda output pins respectively and lose their i/o port functions. r/w is a read/write signal which indicates a read when it is h and a write when it is l. bhe is a byte-high-enable signal which indicates that an odd ad- dress is accessed when it is l. therefore, two bytes at even and odd addresses are accessed si- multaneously when address a 0 is l and bhe is l. ale is an address-latch-enable signal used to latch the address sig- nal from a multiplexed signal of address and data. the latch is open while ale is h, so that the address signal passes through; the ad- dress is held while ale is l. hlda is a hold-acknowledge signal and is used to indicate to the external that the microcomputer accepts hold input and enters hold state. ports p4 0 and p4 1 become hold and rdy input pins, respectively, and their i/o port function are lost. hold is a hold-request signal. it is an input signal used to make the microcomputer enter hold state. hold input is accepted when the f biu has fallen from h to l level while the bus is not used. ports p0, p1, p3 0 and p3 1 enter the floating state while the microcomputer stays in hold state. these ports enter the floating state one cycle of f biu later than hlda signal becomes l level. when terminating hold state, these ports are released from the floating state one cycle of f biu later than hlda signal becomes h level. rdy is a ready signal. when this signal goes l, f cpu and f biu stop at l. rdy is used when a slow external memory is connected, and so on. port p4 2 becomes a normal i/o port when bit 7 of the processor mode register 0 is 0 and becomes the clock f 1 output pin when bit 7 is 1. the f 1 output is independent of rdy and does not stop even when f cpu and f biu stop owing to l input to the rdy pin. processor modes are explained bellow. fig. 86 external memory area for each mode microprocessor mode memory expansion mode ffffff 16 rom ram ram sfr sfr 80 16 2 16 to 9 16 the shaded area is the external memory area. (1) single-chip mode [00] the microcomputer enters the single-chip mode by connecting the cnvss pin to vss and starting from reset. ports p0 to p4 all function as normal i/o ports. port p4 2 can output clock source f 1 by setting bit 7 of the processor mode register 0 to 1. for clock f 1 , refer to fig- ure 82. in this mode, enable signal e is output from pin e. signal e output can be stopped by setting the signal output disable select bit (bit 4 of particular function select register 1) to 1, and it is possible to switch the output to l level. table 8 shows the function of the signal output disable select bits function. (2) memory expansion mode [01] the microcomputer enters the memory expansion mode by setting the processor mode bits to 01 after connecting the cnvss pin to vss and starting from reset. pin e becomes the e output pin. e is an enable signal and is l dur- ing the data/instruction-code-read or data-write term. when the inter- nal memory area is read or written, the e can be fixed to h by setting the signal output disable select bit (bit 4 of particular function select register 1) to 1. port p0 becomes an address output pin, and its i/o port function are lost. port p1 has two functions depending on the level of the byte pin. in both cases, the i/o port function is lost. when the byte pin level is l, port p1 functions as an address out- put pin while e is h and as an odd-address-data i/o pin while e is l. however, if an internal memory area is read, external data is not
73 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (3) microprocessor mode [10] the microcomputer enters the microprocessor mode by connecting the cnvss pin to vcc and starting from reset. it is possible to enter this mode by programming the processor mode bits to 10 after con- necting the cnvss pin to vss and starting from reset. this mode is the same as the memory expansion mode except the following: the internal rom is disabled and an external memory is required, and clock f 1 is always output from port p4 2 independent of bit 7 of the processor mode register 0. as shown in table 8, f 1 output can also be stopped by setting the signal output disable select bit to 1. in this case, write 1 to the port p4 2 direction register bit. table 9 shows the relationship between the cnvss pins input level and the processor modes. table 9. relationship between cnv ss pins input levels and proces- sor modes cnv ss v ss v cc mode ? single-chip ? memory expansion ? microprocessor ? microprocessor description single-chip mode upon start- ing after reset. each mode can be selected by changing the processor mode bits by software. microprocessor mode upon starting after reset.
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 74 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer memory modification function the M37753M8C-XXXFP and m37753m8c-xxxhps internal memory size and address area can be modified by set of bit 2 (memory allocation select bit) of the particular function select regis- ter 0. figure 87 shows the memory allocation when modifying the in- ternal memory area. when ordering a mask rom, mitsubishi electric corp. produces the mask rom using the data within 60 kbytes (between addresses 001000 16 to 00ffff 16 ). it is regardless of the selected rom size (refer to mask rom order confirmation form). therefore, on the eprom tendered for ordering a mask rom, program data ff 16 to addresses which correspond to the area out of the selected rom area. additionally, address 00ffff 16 of the microcomputer corresponds to the lowest address of the tendered eprom. 00 0000 16 00 0080 16 00 087f 16 00 2000 16 00 ffff 16 ff ffff 16 internal rom 60 kbytes internal rom 56 kbytes sfr internal ram 2048 bytes sfr internal ram 2048 bytes 00 0000 16 00 0080 16 00 087f 16 00 1000 16 00 ffff 16 ff ffff 16 external memory area memory allocation select bit = 0 memory allocation select bit = 1 rom size : 56 kbytes ram size : 2048 bytes external memory area note : the internal rom area becomes external memory area in microprocessor mode. fig. 87 memory allocation when modifying internal memory area with memory allocation select bit rom size : 60 kbytes ram size : 2 048 bytes
75 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer addressing modes and instruction set the M37753M8C-XXXFP and m37753m8c-xxxhp have 29 power- ful addressing modes; 1 addressing mode is added to the basis of the 7700 series. refer to the 7751 series software manual for the details. instruction set the M37753M8C-XXXFP and m37753m8c-xxxhp have the ex- tended instruction set; 6 instructions are added to the instruction set of 7700 series. the object code of this extended instruction set is upwards compatible to that of 7700 series instruction set. refer to the 7751 series software manual for the details. shortening number of instruction execution cycles shortening number of instruction execution cycles is realized in the M37753M8C-XXXFP and m37753m8c-xxxhp owing to modifica- tions of the instruction execution algorithm and the cpu circuit, and others. refer to the 7751 series software manual about the number of in- struction execution cycles. data required for mask rom ordering please send the following data for mask orders: <M37753M8C-XXXFP> (1) M37753M8C-XXXFP mask rom order confirmation form (2) 80p6n mark specification form (3) rom data (eprom 3 sets) (1) m37753m8c-xxxhp mask rom order confirmation form (2) 80p6q mark specification form (3) rom data (eprom 3 sets)
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 76 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer absolute maximum ratings recommended operating conditions (vcc = 5 v10 %, ta = C20 to 85 c, unless otherwise noted) notes 1: average output current is the averaage value of a 100 ms interval. 2: the sum of i ol(peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i oh(peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i ol(peak) for ports p4, p5, p6, and p7 must be 110 ma or less, the sum of i oh(peak) for ports p4, p5, p6, and p7 must be 80 ma or less. 3: when the clock source select bit is 1, f(x in )s maximum limit is 12.5 mhz at low-speed running and is 20 mhz at high-speed running. symbol v cc av cc v i v i v o p d t opr t stg parameter power source voltage analog power source voltage input voltage reset, cnv ss , byte input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , v ref , x in output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x out , e power dissipation operating temperature storage temerature unit v v v ratings C0.3 to 7 C0.3 to 7 C0.3 to 12 C0.3 to v cc +0.3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 150 v v mw c c symbol v cc av cc v ss av ss v ih v ih v ih v il v il v il i oh(peak) i oh(avg ) i ol(peak) i ol(peak) i ol(avg) i ol(avg) f(x in ) parameter supply voltage analog supply voltage supply voltage analog supply voltage high-level input voltage p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset, cnv ss , byte high-level input voltage p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) high-level input voltage p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) low-level input voltage p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset, cnv ss , byte low-level input voltage p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) low-level input voltage p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) high-level peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 low-speed running high-speed running limits min. 4.5 0.8 v cc 0.8 v cc 0.5 v cc 0 0 0 ty p. 5.0 v cc 0 0 max. 5.5 v cc v cc v cc 0.2 v cc 0.2 v cc 0.16 v cc C10 C5 10 20 5 15 25 40 unit v v v v v v v v v v ma ma ma ma ma ma mhz low-level peak output current p5 0 Cp5 5 high-level average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 low-level peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 6 , p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 low-level average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 6 , p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 low-level average output current p5 0 Cp5 5 external clock frequency input (note 3)
77 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz (note) ) symbol v oh v oh v oh v ol v ol parameter high-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 power supply current (target value) test conditions i oh = C10 ma i oh = C400 a min. limits 3 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 C0.25 2 ty p. C0.5 max. 2 unit v v v v v v v v v v v a a a ma v note: f(x in ) = 20 mhz when the clock source select bit = 1. v oh v ol v ol v t+ vt C v t+ vt C v t+ vt C i ih i il i oh = C10 ma i oh = C400 a i oh = C10 ma i oh = C400 a i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma i ol = 20 ma i ol = 2 ma 0.45 1.9 0.43 1.6 0.4 2 0.4 v i = 5 v 1 0.5 0.3 i il v i = 0 v 5 C5 v i = 0 v, no pull-up transistor v i = 0 v, pull-up transistor used when clock is stoped. f(x in ) = 40 mhz, square waveform (note) ta = 25 c when clcock is stopped. ta = 85 c when clcock is stopped. output-only pin is open and other pins are vss during reset. a 25 ma C5 C1.0 50 1 20 v ram high-level output voltage p0 0 Cp0 7, p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 , high-level output voltage p3 2 high-level output voltage e low-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 , p4 0 Cp4 7 , p5 6 , p5 7 , p6 0 Cp6 7 ,p7 0 Cp7 7 , p8 0 Cp8 7 low-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 v v ol i ol = 10 ma i ol = 2 ma low-level output voltage p3 2 low-level output voltage e low-level output voltage p5 0 Cp5 5 hysteresis hold, rdy, ta0 in Cta4 in , tb0 in Ctb2 in , int 0 Cint 4 , ad trg , cts 0 , cts 1 , clk 0 , clk 1 , rxd 0 , rxd 1 hysteresis reset, hold, rdy hysteresis x in high-level input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset, cnv ss , byte low-level input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 3 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 1 Cp8 7 , x in , reset, cnv ss , byte low-level input current p5 4 C p5 7 , p8 0 i cc ram hold voltage
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 78 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer a-d converter characteristics (v cc = av cc = 5 v 10 %, v ss = av ss = 0 v, t a = C20 to 85 c, the clock source select bit = 0, unless otherwise noted) unit parameter symbol test conditions limits ty p. min. max. a-d converter selected comparator selected 10-bit mode 8-bit mode comparator 8-bit mode comparator 10-bit mode 8-bit mode comparator 8-bit mode comparator 10-bit mode 8-bit mode comparator r ladder t conv v ref v ia resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage v ref = v cc v ref = v cc v ref = v cc high-speed running (f(x in ) 40 mhz) (note 2) low-speed running (f(x in ) 25 mhz) (note 2) 250 khz f ad 12.5 mhz 250 khz f ad 20 mhz (note 1) f ad = f(x in )/4 selected f ad = f(x in )/2 selected 5 5.9 4.9 1.4 2.45 0.7 4.72 3.92 1.12 2.7 0 10 v ref 3 2 40 3 60 20 v cc v ref 1 256 bits v lsb lsb mv lsb mv k w s v v notes 1 : this is valid when the high-speed running is selected. 2 : when the clock source select bit = 1, f(x in ) is 20 mhz or less at the high-speed running, and f(x in ) is 12.5 mhz or less at the low-speed running. d-a converter characteristics (v cc = 5 v, v ss = av ss = 0 v, v ref = 5 v, t a = C20 to 85 c, unless otherwise noted) unit parameter symbol limits ty p. min. max. test conditions resolution absolute accuracy set time output resistance reference power supply input current t su r o i vref (note) 1 2.5 8 1.0 3 4 3.2 bits % s k w ma note: the test conditions are as follows: ? one d-a converter is used. ? the d-a register value of the unused d-a converter is 00 16 . ? the reference power supply input current of the ladder resistance of the a-d converter is excluded.
79 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer peripheral device input/output timing (v cc = 5 v10 %, v cc = 0 v, t a = C20 to 85 c, unless otherwise noted) * if the values depends on external clock frequency f(x in ), formulas of the limits are shown below. also, the values at f(x in ) = 40 mhz in high- speed running and at f(x in ) = 25 mhz in low-speed running are shown in ( ). at this time, the clock source select bit is 0. when the clock source select bit is 1, regard f(x in ) in tables as 2f(x in ). * the rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. timer a input (up-down input in event counter mode) t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) symbol ta i out input cycle time ta i out input high-level pulse width ta i out input low-level pulse width ta i out input setup time ta i out input hold time parameter limits min. 2000 1000 1000 400 400 max. ns ns ns ns ns unit timer a input (external trigger input in pulse width modulation mode) t w(tah) t w(tal) symbol ta i in input high-level pulse width ta i in input low-level pulse width parameter min. 80 80 limits max. ns ns unit limits symbol parameter min. max. unit 8 10 9 f(x in ) 4 10 9 f(x in ) (200) (160) t c(ta) t w(tah) t w(tal) ta i in input cycle time ta i in input high-level pulse width ta i in input low-level pulse width ns ns ns ns 80 80 timer a input (external trigger input in one-shot pulse mode) limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) (400) (320) (200) (160) (200) (160) f(x in ) 40 mhz (x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz t c(ta) t w(tah) t w(tal) ta i in input cycle time ta i in input high-level pulse width ta i in input low-level pulse width ns ns ns ns ns ns timer a input (gating input in timer mode) note : the tai in input cycle time requires 4 or more cycles of count source. the tai in input high-level pulse width and the tai in input low-level pulse width respectively require 2 or more cycles of the count source. the limits in the table are the values when the count source is f(x in )/4 in high-speed running (f(x in ) 40 mhz) and when the count source is f(x in )/2 in low-speed running (f(x in ) 25 mhz). at this time, the clock source select bit is 0. timer a input (count input in event counter mode) t c(ta) t w(tah) t w(tal) symbol ta i in input cycle time ta i in input high-level pulse width ta i in input low-level pulse width parameter min. 80 40 40 limits max. ns ns ns unit f(x in ) 40 mhz f(x in ) 25 mhz
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 80 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer t c(ta) t su(ta jin -ta jout ) t su(ta jout -ta jin ) symbol parameter min. 800 200 200 limits max. ns ns ns unit timer a input (two-phase pulse input in event counter mode) ta i in input cycle time ta j in input setup time ta j out input setup time tai in input tai out input (up-down input) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) taj in input taj out input test conditions ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, vih = 4.0 v ?up-down and count input in event counter mode ?two-phase pulse input in event counter mode ?count input in event counter mode ?gating input in timer mode ?external trigger input in one-shot pulse mode ?external trigger input in pulse width modulation mode tc (ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in -up) t su(taj in -taj out ) t su(taj in -taj out ) t su(taj out -taj in ) t su(taj out -taj in ) t c(ta) t su(up-t in )
81 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timer b input (count input in event counter mode) symbol tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edge count) tbi in input high-level pulse width (both edge count) tbi in input low-level pulse width (both edge count) parameter limits min. 80 40 40 160 80 80 max. ns ns ns ns ns ns unit limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) (400) (320) (200) (160) (200) (160) f(x in ) 40 mhz f(x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns ns ns ns timer b input (pulse period measurement mode) note : the tbi in input cycle time requires 4 or more cycles of count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of the count source. the limits in the table are the values when the count source is f(x in )/4 in high-speed running (f(x in ) 40 mhz) and when the count source is f(x in )/2 in low-speed running (f(x in ) 25 mhz). at this time, the clock source select bit is 0. limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) (400) (320) (200) (160) (200) (160) f(x in ) 40 mhz f(x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns ns ns ns timer b input (pulse width measurement mode) note : the tbi in input cycle time requires 4 or more cycles of count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of the count source. the limits in the table are the values when the count source is f(x in )/4 in high-speed running (f(x in ) 40 mhz) and when the count source is f(x in )/2 in low-speed running (f(x in ) 25 mhz). at this time, the clock source select bit is 0. t c(ad) t w(adl) symbol ad trg input cycle time (minimum allowable trigger) ad trg input low-level pulse width parameter min. 1000 125 limits max. ns ns unit a-d trigger input
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 82 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) serial i/o symbol clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width t x d i output delay time t x d i hold time r x d i input setup time r x d i input hold time parameter limits min. 200 100 100 0 20 90 max. 80 ns ns ns ns ns ns ns unit t w(inh) t w(inl) symbol int i input high-level pulse width int i input low-level pulse width parameter min. 250 250 limits max. ns ns unit external interrupt int i input t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t h(c - q) t d(c - q) t su(d - c) t w(inh) t w(inl) t h(c - d) t c(ad) t w(adl) tbi in input inti input ad trg input clki txdi rxdi test conditions ?vcc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v,v oh = 2.0 v,c l = 100 pf
83 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer ready, hold timing timing requirements (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 40 mhz when the clock source select bit = 0 * , unless otherwise noted) * the rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. t su(rdy- f 1) t su(hold- f 1) t h( f 1-rdy) t h( f 1-hold) symbol rdy input setup time hold input setup time rdy input hold time hold input hold time parameter limits min. 42 42 0 0 max. ns ns ns ns unit * : f(x in ) = 20 mhz when the clock source select bit = 1. switching characteristics (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 40 mhz when the clock source select bit = 0 * , unless otherwise noted) t d( f 1-hlda) t pxz(hlda-r/wz) t pxz(hlda-bhez) t pxz(hlda-az) t pxz(hlda-a/dz) t pzx(hlda-r/wz) t pzx(hlda-bhez) t pzx(hlda-az) t pzx(hlda-a/dz) symbol hlda output delay time floating start delay time (at hold state) floating start delay time (at hold state) floating start delay time (at hold state) floating start delay time (at hold state) floating release delay time (at hold state) floating release delay time (at hold state) floating release delay time (at hold state) floating release delay time (at hold state) parameter min. limits max. 50 50 50 50 50 ns ns ns ns ns ns ns ns ns unit 0 0 0 0 * : f(x in ) = 20 mhz when the clock source select bit = 1.
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 84 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer rdy input (when 3- f access in high-speed running) hold input test conditions ?v cc = 5 v10 % ? rdy input, hold input : v il = 1.0 v, v ih = 4.0 v ? hlda output : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf f 1 e rdy input t su(rdy- f 1) t h( f 1-rdy) ] rdy input is always sampled at the falling edge of f 1 just before the e signals rise regardless of the bus mode and the number of waits. f 1 hold input hlda output r/w output bhe output a 0 Ca 7 output a 8 Ca 15 output (byte =h) a 16 /d 0 Ca 23 /d 7 a 8 /d 8 Ca 15 /d 15 (byte =l) t su(hold- f 1) t d( f 1-hlda) t pxz(hlda-r/wz) t pxz(hlda-bhe) t pxz(hlda-az) t pxz(hlda-a/dz) t pzx(hlda-r/wz) t pzx(hlda-bhe) t pzx(hlda-az) t pzx(hlda-a/dz) t d( f 1-hlda) t h( f 1-hold) hi-z hi-z hi-z hi-z
85 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer timing requirements (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 40 mhz when the clock source select bit = 0 ] , unless otherwise noted) ] the rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. single-chip mode t c t w(h) t w(l) t r t f t su(pidCe) t h(eCpid) symbol external clock input cycle time (note 1) external clock input high-level pulse width (note 2) external clock input low-level pulse width (note 2) external clock rise time external clock fall time port pi input setup time (i = 08) port pi input hold time (i = 08) parameter min. 25 t c /2 C 8 t c /2 C 8 60 0 limits max. 8 8 ns ns ns ns ns ns ns unit t d(eCpiq) symbol port pi data output delay time (i = 08) parameter min. limits max. 60 ns unit switching characteristics (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 40 mhz when the clock source select bit = 0 ] , unless otherwise noted) (single-chip mode) ] : f(x in ) = 20 mhz when the clock source select bit = 1 notes 1: when the clock source select bit = 1, t c s minimum limit is 50 ns. 2: when the clock source select bit = 1, set t w(h) /t c and t w(l) /t c ratios to 45 to 55 %. ] : f(x in ) = 20 mhz when the clock source select bit = 1 f(x in ) e port pi output (i = 0?) port pi input (i = 0?) t r t f t c t w(h) t w(l) t d(e ?piq) t su(pid ?e) t h(e ?pid) test conditions ?v cc = 5 v?0 % ?intput timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 86 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer timing requirements (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 25 mhz when the clock source select bit = 0 * , unless otherwise noted) ] the rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. memory expansion and microprocessor mode : low-speed running ns ns ns ns ns ns ns ns ns ns unit t c t w(h) t w(l) t r t f t su(dCe) t su(pidCe) t h(eCd) t h(eCpid) t su(an/aCd) symbol external clock input cycle time (note 1) external clock input high-level pulse width (note 2) external clock input low-level pulse width (note 2) external clock rise time external clock fall time data input setup time port pi input setup time (i = 48) data input hold time port pi input hold time (i = 48) data setup time with address stabilized (note 3) parameter min. 40 t c /2 C 8 t c /2 C 8 30 60 0 0 limits max. 8 8 55 (2- f access) 135 (3- f access) 215 (4- f access) * : f(x in ) = 12.5 mhz when the clock source selet bit = 1 notes 1: when the clock source select bit = 1, t c s minimum limit is 80 ns. 2: when the clock source select bit = 1, set t w(h) /t c and t w(l) /t c ratios to 45 to 55 %. 3: since the values depend on external clock input frequency f(x in ), calculate them using the bus timing data formula on the page after the next page.
87 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer f high-level pulse width, f low-level pulse width (note) f 1 output delay time e low-level pulse width (note) address output delay time (note) data output delay time floating start delay time address output delay time (note) address output delay time (note) ale output delay time (note) ale output delay time ale pulse width (note) bhe output delay time (note) r/w output delay time (note) address hold time (note) address hold time data hold time (note) floating release delay time (note) bhe hold time (note) r/w hold time (note) port pi data output delay time (i = 48) switching characteristics (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 25 mhz when the clock source select bit = 0 * , unless otherwise noted) memory expansion and microprocessor mode : low-speed running symbol parameter unit t w( f h) , t w( f l) t d(eC f 1) t w(el) t d(anCe) t d(eCdq) t pxz(eCdz) t d(aCe) t d(aCale) t d(eCale) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe) t h(eCan) t h(aleCa) t h(eCdq) t pzx(eCdz) t h(eCbhe) t h(eCr/w) t d(eCpiq) min. 20 C12 55 12 12 5 20 4 22 15 15 10 9 18 18 10 10 2- f access max. 7 35 5 60 3- f access min. 20 C12 135 12 12 5 20 4 22 15 15 10 9 18 18 10 10 max. 7 35 5 60 min. 20 C12 135 92 92 52 20 4 62 95 95 10 25 (note) 18 18 10 10 4- f access max. 7 35 5 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns * : f(x in ) = 12.5 mhz when the clock source selet bit = 1 note: since the values depend on external clock input frequency f(x in ), calculate them using the bus timing data formula on the next page. the value of t h(aleCa) depends on f(x in ) only when 4C f access is performed.
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 88 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer data setup time with address stabilized f high-level pulse width, f low-level pulse width e low-level pulse width address output delay time address output delay time address output delay time ale output delay time ale pulse width bhe outupt delay time r/w output delay time address hold time address hold time data hold time floating release delay time bhe hold time r/w hold time bus timing data formulas memory expansion and microprocessor mode : low-speed running (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) 25 mhz when the clock source select bit = 0 * , unless otherwise noted) ] : f(x in ) 12.5 mhz when the clock source select bit = 1 note: when the clock source select bit is 1, regard f(x in ) in tables as 2f(x in ). 4- f access symbol t su(an/aCd) t w ( f h) ,t w( f l) t w(el) t d(anCe) t d(aCe) t d(aCale) t d(eCale) t w(ale) t d(bheCe) t d(r/wCe) t h(eCan) t h(aleCa) t h(eCdq) t pzx(eCdz) t d(eCbhe) t d(eCr/w) parameter 2- f access 3- f access ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit 5 10 9 f(x in ) C65 4 10 9 f(x in ) C25 7 10 9 f(x in ) C65 3 10 9 f(x in ) C28 3 10 9 f(x in ) C28 2 10 9 f(x in ) C28 2 10 9 f(x in ) C18 3 10 9 f(x in ) C25 3 10 9 f(x in ) C25 1 10 9 f(x in ) C15 3 10 9 f(x in ) C65 1 10 9 f(x in ) C20 2 10 9 f(x in ) C25 1 10 9 f(x in ) C28 1 10 9 f(x in ) C28 1 10 9 f(x in ) C35 1 10 9 f(x in ) C20 1 10 9 f(x in ) C18 1 10 9 f(x in ) C25 1 10 9 f(x in ) C25 1 10 9 f(x in ) C30 1 10 9 f(x in ) C22 1 10 9 f(x in ) C22 1 10 9 f(x in ) C30 1 10 9 f(x in ) C30
89 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t h(e-dq) t d(e-dq) t d(a-ale) t h(ale-a) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t d(e-piq) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 15 /d 15 output (byte =?? ale output bhe output address address data r/w output port pi output (i = 4?) d 0 ? 7 input d 8 ? 15 input (byte =?? (when 2- f access in low-speed running )
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 90 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 2- f access in low-speed running ) test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t pxz(e-dz) t d(a-ale) t h(ale-a) t su(d-e) t su(an/a-d) t pzx(e-dz) t h(e-d) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t h(e-pid) t su(pid-e) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi input (i = 4?) a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 16 /d 16 output (byte =?? d 0 ? 7 input d 8 ? 15 input (byte =??
91 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 3- f access in low-speed running ) f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t h(e-dq) t d(e-dq) t d(a-ale) t h(ale-a) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t d(e-piq) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi output (i = 4?) a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 15 /d 15 output (byte =?? d 0 ? 7 input d 8 ? 15 input (byte =?? test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 92 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 3- f access in low-speed running ) f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t pxz(e-dz) t pzx(e-dz) t d(a-ale) t h(ale-a) t su(d-e) t su(an/a-b) t h(e-d) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t h(e-pid) t su(pid-e) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi input (i = 4?) a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 16 /d 16 output (byte =?? d 0 ? 7 input d 8 ? 15 input (byte =?? test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
93 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 4- f access in low-speed running ) f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t h(e-dq) t d(e-dq) t d(a-ale) t h(ale-a) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t d(e-piq) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi output (i = 4?) a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 15 /d 15 output (byte =?? d 0 ? 7 input d 8 ? 15 input (byte =?? test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 94 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 4- f access in low-speed running ) f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t pzx(e-dz) t h(e-d) t pxz(e-dz) t d(a-ale) t h(ale-a) t su(d-e) t su(an/a-d) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t su(pid-e) t h(e-pid) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi input (i = 4?) a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 16 /d 16 output (byte =?? d 0 ? 7 input d 8 ? 15 input (byte =?? test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
95 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer min. 25 t c /2 C 8 t c /2 C 8 30 60 0 0 external clock input cycle time (note 1) external clock input high-level pulse width (note 2) external clock input low-level pulse width (note 2) external clock rise time external clock fall time input setup time port pi input setup time (i = 48) data input hold time port pi input hold time (i = 48) data setup time with address stabilized (note 3) timing requirements (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in )=40 mhz when the clock source select bit = 0 * , unless otherwise noted) ] the rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. memory expansion and microprocessor mode : high-speed running t c t w(h) t w(l) t r t f t su(dCe) t su(pidCe) t h(eCd) t h(eCpid) t su(an/a-d) symbol parameter limits max. 8 8 ns ns ns ns ns ns ns ns ns ns unit 50 (3- f access) 100 (4- f access) 150 (5- f access) * : f(x in ) = 20 mhz when the clock source selet bit = 1 notes 1: when the clock source select bit = 1, t c s minimum limit is 50 ns. 2: when the clock source select bit = 1, set t w(h) /t c and t w(l) /t c ratios to 45 to 55 %. 3: since the values depend on external clock input frequency f(x in ), calculate them using the bus timing data formula on the page after the next page.
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 96 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer switching characteristics (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 40 mhz when the clock source select bit = 0 * , unless otherwise noted) memory expansion and microprocessor mode : high-speed running symbol parameter unit t w( f h) , t w( f l) t d(eC f 1) t w(el) t d(anCe) t d(eCdq) t pxz(eCdz) t d(aCe) t d(aCale) t d(eCale) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe) t h(eCan) t h(aleCa) t h(eCdq) t pzx(eCdz) t h(eCbhe) t h(eCr/w) t d(eCpiq) f high-level pulse width, f low-level pulse width f 1 output delay time e low-level pulse width address output delay time data output delay time floating start delay time address output delay time address output delay time ale output delay time ale output delay time ale pulse width bhe output delay time r/w output delay time address hold time address hold time data hold time floating release delay time bhe hold time r/w hold time port pi data output delay time (i = 4C8) min. 5 C12 50 15 15 5 10 4 10 20 20 10 10 15 15 10 10 3- f access max. 7 35 5 60 4- f access min. 5 C12 75 40 40 30 10 4 35 45 45 10 10 15 15 10 10 max. 7 35 5 60 min. 5 C12 125 40 40 30 10 4 35 45 45 10 10 15 15 10 10 5- f access max. 7 35 5 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) * : f(x in ) = 20 mhz when the clock source selet bit = 1 note: since the values depend on external clock frequency f(x in ), calculate them by using the bus timing data formulas on the next page.
97 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer 5 10 9 f(x in ) C75 1 10 9 f(x in ) C20 3 10 9 f(x in ) C25 2 10 9 f(x in ) C35 2 10 9 f(x in ) C35 1 10 9 f(x in ) C20 1 10 9 f(x in ) C15 1 10 9 f(x in ) C15 2 10 9 f(x in ) C30 2 10 9 f(x in ) C30 1 10 9 f(x in ) C15 1 10 9 f(x in ) C15 1 10 9 f(x in ) C10 1 10 9 f(x in ) C10 1 10 9 f(x in ) C15 1 10 9 f(x in ) C15 t su(an/aCd) t w( f h) , t w( f l) t w(el) t d(anCe) t d(aCe) t d(aCale) t d(eCale) t w(ale) t d(bheCe) t d(r/wCe) t h(eCan) t h(aleCa) t h(eCdq) t pzx(eCdz) t d(eCbhe) t d(eCr/w) symbol data setup time with address stabilized f high-level pulse width, f low-level pulse width e low-level pulse width address output delay time address output delay time address output delay time ale outuput delay time ale pulse width bhe outuput delay time r/w outuput delay time address hold time address hold time data hold time floating release delay time bhe hold time r/w hold time parameter 3- f access 4- f access unit 5- f access bus timing data formulas memory expansion and microprocessor mode : high-speed running (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) 40 mhz when the clock source select bit = 0 * , unless otherwise noted) ] : f(x in ) 20 mhz when the clock source select bit = 1 note: when the clock source select bit is 1, regard f(x in ) in tables as 2f(x in ). ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 10 9 f(x in ) C75 4 10 9 f(x in ) C25 3 10 9 f(x in ) C35 3 10 9 f(x in ) C35 2 10 9 f(x in ) C20 2 10 9 f(x in ) C15 3 10 9 f(x in ) C30 3 10 9 f(x in ) C30 9 10 9 f(x in ) C75 6 10 9 f(x in ) C25
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 98 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 3- f access in high-speed running ) f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t h(e-dq) t d(e-dq) t d(a-ale) t h(ale-a) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t d(e-piq) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi output (i = 4?) a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 15 /d 15 output (byte =?? d 0 ? 7 input d 8 ? 15 input (byte =?? test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
99 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 3- f access in high-speed running ) f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t pzx(e-dz) t pxz(e-dz) t d(a-ale) t h(ale-a) t su(d-e) t h(e-d) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t h(e-pid) t su(pid-e) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi input (i = 4?) a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 16 /d 16 output (byte =?? d 0 ? 7 input d 8 ? 15 input (byte =?? t su(an/a-d) test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 100 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 4- f access in high-speed running ) f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t h(e-dq) t d(e-dq) t d(a-ale) t h(ale-a) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t d(e-piq) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi output (i = 4?) a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 15 /d 15 output (byte =?? d 0 ? 7 input d 8 ? 15 input (byte =?? test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
101 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 4- f access in high-speed running ) f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t pzx(e-dz) t pxz(e-dz) t d(a-ale) t h(ale-a) t su(d-e) t h(e-d) t w(ale) t su(an/a-d) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t h(e-pid) t su(pid-e) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi input (i = 4?) a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 16 /d 16 output (byte =?? d 0 ? 7 input d 8 ? 15 input (byte =?? test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 102 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 5- f access in high-speed running ) f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t h(e-dq) t d(e-dq) t d(a-ale) t h(ale-a) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t d(e-piq) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi output (i = 4?) a 0 ? 7 output a 8 ? 15 output (byte =?? a 16 /d 0 ? 23 /d 7 output a 8 /d 8 ? 15 /d 15 output (byte =?? d 0 ? 7 input d 8 ? 15 input (byte =?? test conditions (port pi, f(x in )) ?v cc = 5 v?0 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v?0 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
103 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer (when 5- f access in high-speed running ) f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t pxz(e-dz) t pxz(e-dz) t d(a-ale) t h(ale-a) t su(d-e) t h(e-d) t w(ale) t su(an/a-d) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t h(e-pid) t su(pid-e) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e ale output bhe output address address data r/w output port pi input (i = 4 ~ 8) a 0 Ca 7 output a 8 Ca 15 output (byte =h) a 16 /d 0 Ca 23 /d 7 output a 8 /d 8 Ca 16 /d 16 output (byte =l) d 0 Cd 7 input d 8 Cd 15 input (byte =l) test conditions (port pi, f(x in )) ? v cc = 5 v10 % ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ? v cc = 5 v10 % ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ? data input : v il = 0.8 v, v ih = 2.5 v
mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp 104 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer f high-level pulse width, f low-level pulse width f 1 output delay time e low-level pulse width address output delay time floating start delay time (byte=l) address output delay time address output delay time ale output delay time ale output delay time ale pulse width bhe output delay time r/w output delay time address hold time address hold time (byte=l) floating release delay time (byte=l) bhe hold time r/w hold time t w( f h) , t w( f l) t d(eC f 1 ) t w(el) t d(anCe) t pxz(eCdz) t d(aCe) t d(aCale) t d(eCale) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe) t h(eCan) t h(aleCa) t pzx(eCdz) t d(eCbhe) t d(eCr/w) symbol parameter unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns C 20 C20 C 35 C 35 C 20 C 15 C 15 C 30 C 30 C 15 C 15 C 10 C 15 C 15 min. limits 5 C12 5 15 15 5 10 4 10 20 20 10 10 15 10 10 max. 7 5 bus timing data formula 1 10 9 f(x in ) 1 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) * : f(x in ) 20 mhz when the clock source select bit = 1. external bus timing when internal memory area is accessed (2- f access) in high-speed running (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) 40 mhz when the clock source select bit = 0 * )
105 mitsubishi microcomputers M37753M8C-XXXFP, m37753m8c-xxxhp m37753s4cfp, m37753s4chp preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer f(x in ) t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t d(a-ale) t h(ale-a) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c f 1 e a 0 Ca 7 output a 8 Ca 15 output (byte =h) ale output bhe output address address data t w(l) t w( f l) t w( f h) t w(el) t d(e- f 1) t d(an-e) t h(e-an) t pxz(e-dz) t pzx(e-dz) t d(a-ale) t h(ale-a) t w(ale) t d(ale-e) t d(e-ale) t d(bhe-e) t h(e-bhe) t h(e-r/w) t d(r/w-e) t d(a-e) t d(e- f 1) t w(h) t r t f t c address address r/w output d 0 Cd 7 input d 8 Cd 15 input (byte =l) the value of write data is undefined. contents of external data bus cannot be read into the internal. write read a 16 /d 0 Ca 23 /d 7 output a 8 /d 8 Ca 15 /d 15 output (byte =l) test conditions ? v cc = 5 v10 % ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf (external bus timing on internal ram access (2- f access) in high-speed running) <> <> h h
single-chip 16-bit microcomputer M37753M8C-XXXFP date: receipt gzzCsh00C83b<85a0> ( ) note : please fill in all items marked customer supervisor company name date issued date: tel 1. confirmation specify the name of the product being ordered. three sets of eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contai n the identical data, we will produce masks based on this da ta. we shall assume the responsibility for errors only if the ma sk rom data on the products we produce differ from this data . thus, the customer must be especially careful in verifying t he data contained in the eproms submitted. checksum code for entire eprom areas eprom type : (hexadecimal notation) responsible officer section head signature supervisor signature issuance signatures one of the following sets of data should be written to the o ption data address (10 16 ) of the eprom you have ordered. check @ in the appropriate box. stp instruction enable stp instruction disable 2. stp instruction option 01 16 00 16 address 10 16 address 10 16 3. mark specification mark specification must be submitted using the correct form for the type of package being ordered fill out the appropria te 80p6n mark specification form (for M37753M8C-XXXFP), 80p6q m ark specification form (for m37753m8c-xxxhp) and attach to the mask rom order confirmation form. 7700 family mask rom order confirmation form mask rom number mitsubishi electric m37753m8c-xxxhp ffff 0010 0000 (1) set ff 16 in the shaded area. (2) address 0 16 to 10 16 are the area for storing the data on model designation and options.this area must be written with the data shown below. details for option data are given next in the section describing the stp instruction option. address and data are written in hexadecimal notation. 0 3 7 5 2 f a e c b 9 8 d 4 1 6 4d 33 37 37 33 4d 35 43 2d ff ff ff ff ff ff option data address address address 38 10 4. comments 1000 data 60k 1ffff 00010 00000 11000 data 60k 27101 27512
1 80 65 40 64 41 25 24 mitsubishi product number (6-digit, or 7-digit) 1 80 65 40 64 41 25 24 customers parts number note : the fonts and size of characters are standard mitsubishi type. mitsubishi ic catalog name notes 1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. 3 : customers parts number can be up to 14 alphanumeric char- acters for capital letters, hyphens, commas, periods and so on. 4 : if the mitsubishi logo is not required, check the box below. mitsubishi logo is not required 80p6n (80-pin qfp) mark specification form mitsubishi ic catalog name please choose one of the marking types below (a, b, c), and enter the mitsubishi ic catalog name and the special mark (if neede d). a. standard mitsubishi mark c. special mark required b. customers parts number + mitsubishi ic catalog name mitsubishi ic catalog name notes1 : if special mark is to be printed, indicate the desired lay- out of the mark in the left figure. the layout will be duplicated technically as close as possible. mitsubishi product number (6-digit, or 7-digit) and mask rom number (3-digit) are always marked for sorting the products. 2 : if special character fonts (e,g., customers trade mark logo) must be used in special mark, check the box be- low. for the new special character fonts, a clean font original (ideally logo drawing) must be submitted. special character fonts required 1 80 65 40 64 41 25 24
? 1999 mitsubishi electric corp. new publication, effective apr. 1999. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our cu stomers in the selection of the mitsubishi semiconductor pro duct best suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility fo r any damage, or infringement of any third-party s rights, originating in the use of any product data, diagra ms, charts or circuit application examples contained in these materials. ? all information contained in these materials, including prod uct data, diagrams and charts, represent information on prod ucts at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improveme nts or other reasons. it is therefore recommended that custo mers contact mitsubishi electric corporation or an authorize d mitsubishi semiconductor product distributor for the latest product information befor e purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not desig ned or manufactured for use in a device or system that is us ed under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use o f a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. ? the prior written approval of mitsubishi electric corporatio n is necessary to reprint or reproduce in whole or in part t hese materials. ? if these products or technologies are subject to the japanes e export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control law s and regulations of japan and/or the country of destination is prohibited. ? please contact mitsubishi electric corporation or an authori zed mitsubishi semiconductor product distributor for further details on these materials or the products contained therei n. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when m aking your circuit designs, with appropriate measures such a s (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mish ap.
rev. rev. no. date 1.0 first edition 971114 1.01 the following are added: 980528 ?mask rom order confirmation form ?mark specification form 2.00 (1) for the valid output polarity select bit for interrupt request (bit 1 at address 1c 16 ) (three- 990428 phase mode 1), its name and function are corrected: ? new bit name in three-phase mode 1: interrupt validity output select bit ? corrected function: 0: timer b2 interrupt request generated at each even-numbered underflow of timer b2 1: timer b2 interrupt request generated at each odd-numbered underflow of timer b2 ? related pages: pages 36, 37, 39 (2) for the following register, its internal status after reset is corrected: ? target register: port p2 direction register (address 08 16 ) ? correction: the status of bits 4 to 6 is 000. (not .) ? related page: page 62 (3) for the following register, its internal status after reset is corrected: ? target register: processor mode register 0 (address 5e 16 ) ? correction: the status of bit 1 is 0. (not 1.) ? related page: page 62 (4) the names of registers at addresses 5c 16 , 5d 16 are corrected: ? address 5c 16 : timer b 1 mode register ? address 5d 16 : timer b 2 mode register ? related page: page 62 (5) for the timer a write flag (address 45 16 ), its name and its bit name are corrected: ? new register name: timer a write register ? new bit name: timer ai write bit (i = 0 to 2) ? related pages: pages 7, 36, 39, 62 revision description list M37753M8C-XXXFP/hp data sheet (1/1) revision description

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